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Registered: ‎07-15-2019

Vivado HLS generates syntax error-Verilog code

When I use array in SystemC, a problem was happened.

If I use array in SC_MODULE, Vivado HLS 2019.2 generates syntax error-Verilog codes.

 

such as

In SystemC, as follows,

sc_uint<4> X[4];

and in generated Verilog, as follows, waste "end" is the error 

always @(*)begin
  *****
end
end

Arrays are not surported in SystemC?

Please tell me how to use array with no syntax error-Verilog code.

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