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Visitor memoryzpp
Registered: ‎02-03-2013

Vivado_HLS pcore stops work when accessing AXI Bus

I am using vivado_hls to synthesize a pcore with a very simple function: use memcpy to move data from one ap_bus port to another ap_bus port. The two bus ports are mapped to AXI bus interfaces and attached to the system AXI bus in the default EDK environment with single Microblaze on ML605 board. A single pcore can finish job (indicated by ap_done and ap_idle signal). But problem comes when I duplicate the pcore into 6 instances and put them all in the system (attached to the same system AXI bus). After I start the six instances simultaneouosly, two of them just get stalled (ap_idle signal keeps low forever).

Does anyone know the reason of this problem and how to solve this problem so that I could use 6 pcores in the system at the same time? Thank you very much!


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Xilinx Employee
Xilinx Employee
Registered: ‎08-17-2011

Re: Vivado_HLS pcore stops work when accessing AXI Bus

Greetings, a few questions/pointers...
1- How do you debug that?
2- Did you run any simulation?
3- You went from 1 to 6 pcores, any chances you tried with 2, then 3?
4- If using memcpy you intend to use burst on AXI4 "full", not AXI4 Lite, right? -> so did you check your interconnects?
- Hervé

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Visitor alondight
Registered: ‎12-28-2012

Re: Vivado_HLS pcore stops work when accessing AXI Bus

Thank you very much for your points, here are some clarifications:

1 - We use xmd to connect mb mdm and dowload elf for debugging. In the elf, we set the ap_start signals of the six pcore instances to high by writing to their slave addresses on the AXIlite bus and then poling the AXIlite bus until all their idle bits go high (AXIlite bus is used to send ap_start/ap_idle signals only, irrelevant to data transfer).

2 - We did not run simulation yet. However simulation might not help since the phenomenon observed by us is nondeterministic: sometimes the two of the six instances get stalled in the first execution, sometimes they do not get stalled until several times of the execution are repeated (we use a for loop in the elf to repeat the process of setting ap_start and checking ap_idle). In the xmd, just stop and run the processor again will get this variation.

3 - When the number of pcores is 1~5, everything is okay. problems emerge when we increase the number to six.

4 - Of course memcpy goes to AXI4 full, not AXI4 lite. Actually the pcore implemented by us is to move data from one address of the offchip DRAM via private buffer to another address of the offchip DRAM. AXI4 lite has no access to DDR. We do verify the correctness of data when the system works with 1~5 pcore instances. So I believe that the function of our system and modules is correct.


Thank you very much!

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