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Visitor
Visitor
8,178 Views
Registered: ‎03-26-2014

Vivado HLS scheduler taking hours

Hi all,

 

I'm trying to synthesize a simple kernel with Vivado HLS. The vanilla kernel with no pragmas synthesizes fine. However, when I add a few pragmas (loop unroll, pipeline) to unroll and pipeline the loops, the HLS synthesis gets stuck at scheduling. I've waited for more than two hours, and this has happened on multiple occasions. There is no error, just that the logging doesn't progress beyond "Starting scheduling ...".

 

I am hoping that the community has seen something like this in the past. Do you have any pointers on what might be happening? Is there any way to see a more detailed/verbose log from Vivado HLS? I've attached my HLS design file. Any pointers?

 

Thanks,

Raghu

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Xilinx Employee
Xilinx Employee
8,170 Views
Registered: ‎03-24-2010

I suspect that with PIPELINE and UNROLL, HLS need put much more effort to shedule and hit the bottleneck of a cpu/memory requirement. You may evaluate if it's possible to remove some of PIPELINE/UNROLL directives.

Regards,
brucey
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Moderator
Moderator
8,142 Views
Registered: ‎04-17-2011

@raghup17 

Do you have any further questions? If in case any of the above topic helped then please feel free to mark it as an accepted solution.

Regards,
Debraj
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Visitor
Visitor
8,137 Views
Registered: ‎03-26-2014

I'm running HLS on a big server machine with 16 Xeon cores and about 100GB of DRAM, so I doubt if it is a memory/compute requirement. Perhaps the scheduler is taking far too long to converge? 

 

Anyway, I modified my design to unroll only 2 times instead of complete unrolling, and the HLS synthesizes successfully. This is not what I would want to do, but looks like I've to live with it to get Vivado HLS to pass scheduling.

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Moderator
Moderator
8,114 Views
Registered: ‎04-17-2011

@raghup17 Thanks for sharing the solution also. Please feel to accept your post as a solution for other community users.

Regards,
Debraj
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Observer
Observer
8,108 Views
Registered: ‎03-27-2014

I also have designs projects currently run overnight to synthetizie with a medium-size configuration, but take a lot longer when I modify some #defines which cause e.g. unrolled loops to iterate 100 instead of 50 times - therefore I guess some algorithms are o(n^>=2).

 

I also noticed synthetizing is only single-threaded, as only a single core is loaded 100% during a HLS run.


It would be great if Vivado could use multiple threads/cores for the most time consuming parts of it`s HLS process, as currently single-threaded performance of current processors seems to stay rather flat - more money most of the time buys you only more cores. I already thought about buying an AMD FX-9590, as it can Turbo to 5Ghz.

 

Regards, Clemens

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Moderator
Moderator
8,101 Views
Registered: ‎04-17-2011

@linuxhippy Please create a new topic with you query.

Regards,
Debraj
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