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Visitor linchpin_k
Visitor
262 Views
Registered: ‎06-30-2019

Vivado HLS synthesis is not processing from when pipelining scheduling.

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Hi all. I have a problem about HLS synthesis.

I've designed .cpp in Vivado HLS 2018.3 for my hardware accelerator.
And I performed 'generate bitstream' and bare-metal test on Vivado and Vivado SDK.
After then, for the optimization, I added one more loop on my .cpp code in HLS.

However, C synthesis is not processing from pipeline loop scheduling.


Following code is brief structure of my code:
struct data_struct{
    float data;
    bool last;
}

void my_acc(hls::stream<float> &input, hls::stream<data_struct> &output){
    float in_a[100], in_b[100], out[100];
    int i;
    struct data_struct out_data;

#pragma HLS INTERFACE axis port = input
#pragma HLS INTERFACE axis port = output
#pragme HLS INTERFACE s_axilite port = return bundle = CRTLS_BUS

    READ_IN1:
    for(i=0; i<100; ++i){
#pragma HLS PIPELINT II = 1
        in_a[i] = input.read( );
    }
    READ_IN2:
    for(i=0; i<100; ++i){
#pragma HLS PIPELINT II = 1
        in_b[i] = input.read( );
    }

    LOOP_H:
    for(int h = 0; h < 31; ++h){
        LOOP_W:
        for(int w = 0; w < 31; ++w){
            LOOP_C:
            for(int c = 0; c < 1000; ++c){
                LOOP_S:
                for(int s = 0; s < 256; ++s){
                    // do something;
                }
            }
            LOOP_R:
            for(int r = 0; r < 500; ++r){
                // do something
            }
        }
    }
    
    LOOP_WRITE:
    for(i=0; i<100; ++i){
#pragma HLS PIPELINE II = 1
    out_data.data = out[i];
    out_data.last = (i == 99) ? 1 : 0;
    output.write(out_data);
    }
}

I performed bare-metal test without the loop labled LOOP_R without any problems .

After addition of the LOOP_R, however, C synthesis stops duiring its process.
For example, the last console report is:
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-61] pipelining loop 'READ_IN1'

From here, the C cynthesis doen not processed after one day...

I have no idea why C synthesis stops during processing when I insert a new loop.

Please advice for me.

Thank you.

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1 Solution

Accepted Solutions
Visitor linchpin_k
Visitor
91 Views
Registered: ‎06-30-2019

Re: Vivado HLS synthesis is not processing from when pipelining scheduling.

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I solved this problem.

I think synthesis consume too long time due to complex logic.

I use any completely partitioned buffers so that it requires logic complexity such as complex connection, memory port, etc.

But I changed partition type and partition factor from completely partition to cyclic 16 partition.

Then, I successed HLS systhesis without any errors.

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3 Replies
Xilinx Employee
Xilinx Employee
229 Views
Registered: ‎07-21-2014

Re: Vivado HLS synthesis is not processing from when pipelining scheduling.

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Hi,

 

I am unable to reproduce the issue with simple assignments inside the loops.

Can you let us know the operations that you are performing? If you can attach the code to reproduce the issue that would be helpful.

 

-Shreyas

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Moderator
Moderator
150 Views
Registered: ‎11-21-2018

Re: Vivado HLS synthesis is not processing from when pipelining scheduling.

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Hi @linchpin_k 

Do you have any update on this? 

Regards, 

 

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Visitor linchpin_k
Visitor
92 Views
Registered: ‎06-30-2019

Re: Vivado HLS synthesis is not processing from when pipelining scheduling.

Jump to solution

I solved this problem.

I think synthesis consume too long time due to complex logic.

I use any completely partitioned buffers so that it requires logic complexity such as complex connection, memory port, etc.

But I changed partition type and partition factor from completely partition to cyclic 16 partition.

Then, I successed HLS systhesis without any errors.

0 Kudos