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Contributor
Contributor
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Registered: ‎12-24-2009

Vivado HlS - getting a handle on simple AXI Lite Slave with small arrays

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I have a function I want to implement

 

void corey_sample_function( uint32 a[8], uint32 b[3], uint32 *c, int *d)

 

a and b are input

c and d are output

 

I want just a simple AXI Lite interface to load the arrays in A and B.   Touch ap_start, wait and then read c and d.

 

If I implement all 4 interfaces as ap_hs and then select the AXI LITE as the resource I get this C interface file with the memory mapping for my Zynq pcore.

 

// 0x00 : Control signals
// bit 0 - ap_start (Read/Write/SC)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// others - reserved
// 0x04 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x08 : IP Interrupt Enable Register (Read/Write)
// bit 0 - Channel 0 (ap_done)
// others - reserved
// 0x0c : IP Interrupt Status Register (Read/TOW)
// bit 0 - Channel 0 (ap_done)
// others - reserved
// 0x10 : Control signal of a
// bit 0 - a_ap_vld (Read/Write/COH)
// bit 1 - a_ap_ack (Read)
// others - reserved
// 0x14 : Data signal of a
// bit 31~0 - a[31:0] (Read/Write)
// 0x18 : Control signal of b
// bit 0 - b_ap_vld (Read/Write/COH)
// bit 1 - b_ap_ack (Read)
// others - reserved
// 0x1c : Data signal of b
// bit 31~0 - b[31:0] (Read/Write)
// 0x20 : Control signal of c
// bit 0 - c_ap_vld (Read)
// bit 1 - c_ap_ack (Read/Write/COH)
// others - reserved
// 0x24 : Data signal of c
// bit 31~0 - c[31:0] (Read)
// 0x28 : Control signal of d
// bit 0 - d_ap_vld (Read)
// bit 1 - d_ap_ack (Read/Write/COH)
// others - reserved
// 0x2c : Data signal of d
// bit 31~0 - d[31:0] (Read)
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)

 

I do not see how this interface can possible index into an array of 8 elements and 3 elements.  What am I missing?

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Highlighted
Contributor
Contributor
7,602 Views
Registered: ‎12-24-2009

Re: Vivado HlS - getting a handle on simple AXI Lite Slave with small arrays

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Ok found my answer.

 

Starting at page 160 of UG902 the guide talks about "complete" array partitioning.  Exactly what I want.  Breaking up the arrays for the AXI4 interface and give seperate addresses to all the inputs of the array.

 

 Wish this note was in the "interfaces" section of the User Guide!

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Highlighted
Contributor
Contributor
7,603 Views
Registered: ‎12-24-2009

Re: Vivado HlS - getting a handle on simple AXI Lite Slave with small arrays

Jump to solution

Ok found my answer.

 

Starting at page 160 of UG902 the guide talks about "complete" array partitioning.  Exactly what I want.  Breaking up the arrays for the AXI4 interface and give seperate addresses to all the inputs of the array.

 

 Wish this note was in the "interfaces" section of the User Guide!

View solution in original post

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Anonymous
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5,026 Views

Re: Vivado HlS - getting a handle on simple AXI Lite Slave with small arrays

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Hi there,

 

Usefull question and commment.

 

Was wondeirng has anyone tried the other way around? meaning to generate array output?

and if yes, how can you capture it in the main file?

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