UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Adventurer
Adventurer
417 Views
Registered: ‎04-25-2017

Vivado hls synthesis is hanging in 2018.2, but finishing succesfully in 2017.2

Hi,

1. I am synthesizing a code in vivado hls 2018.2 which contains two arrays each of size 256 elements. To achieve initiation interval 1, I am using

   #pragma HLS ARRAY_PARTITION.   Initiation interval 1 is achieved, but synthesis is hanging during RTL generation. However, in vivado hls 2017.2 synthesis is finishing succesfully with initiation interval 1.

2.  In 2017.2, we were defining pipeline pragma inside our operator function and data flow pragma in our top function definition and we were obtaining initiation interval 1. But In 2018.2, although we are doing the same thing, initiation interval is not getting 1 for the same code. Thus, we tried avoiding the usage of data flow pragma in our codes while using 2018.2 and kept pipeline pragma in top function. By doing so, we got II = 1 . Can any one tell me why is this happening ?

0 Kudos
1 Reply
Highlighted
Adventurer
Adventurer
402 Views
Registered: ‎04-25-2017

Re: Vivado hls synthesis is hanging in 2018.2, but finishing succesfully in 2017.2

@bevinamarPlease look into this.

0 Kudos