I'm running the Vivado HLS tool at <INSTALLDIR>/Vivado_HLS/2012.3/Linux_x86_64/bin/vivado_hls_bin on 64-bit Ubuntu.
When I convert a top-level function with pointer arguments marked as an "ap_bus" the address from C to Verilog the address lines always come out to be 32 bits wide. UG902 mentioned context sensitive results for the width of the data type "long" on 32-bit versus 64-bit systems. When using a "long" variable in HLS I get a 64-bit variable but always 32-bit addresses.
Is there a workaround for this using "ap_bus" or will I have to specify a custom interface? Would that even solve the issue?
Workarounds like dropping to 32-bit software or performing memory accesses without delay aren't an option since I'm trying to accelerate programs written to interoperate with a 64-bit CPU/OS/software.