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Adventurer
Adventurer
375 Views
Registered: ‎07-27-2018

Wait for external signal trigger in HLS block

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Hi everybody,

I have a simple dubt, my main question is about wait on external signal.

I'm implementing a startup process for 100G Ethernet peripheral, the actions to perform are explained in PG165 v2.5:

1. Write the below registers:
    0x00014 : 32'h00000001 [CONFIGURATION_RX_REG1 for ctl_rx_enable]
    0x0000C : 32'h00000010 [CONFIGURATION_TX_REG1 for ctl_tx_send_rfi]
2. Wait for RX_aligned then write the below registers:
    0x0000C : 32'h00000001 [CONFIGURATION_TX_REG1 for ctl_tx_enable to 1’b1 and
    ctl_tx_send_rfi to 1’b0]

I would implement this like:

void CMAC_Ctrl(volatile uint32_t * ptrCMACport, uint1 RX_aligned)
{


#pragma HLS INTERFACE s_axilite port=ptrCMACport offset=off depth=1024

// write on ptrCMACport

while(RX_aligned != 0b1){};

// write on ptrCMACport


}

My question/dubt is:

Is the while construct valid to wait an external signal inside an HLS block?

Since the HLS block is executed once the ap_start is asserted how can it refresh the rx_aligned?

Please suggest me an approach, in vhdl is very simple task but since many IP are moving toward AXI control interface

I would like to understand how this situation can be managed with HLS, or if HLS is not the suitable technology.

Thank you

 

 

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1 Solution

Accepted Solutions
Observer nikhilghanathe
Observer
339 Views
Registered: ‎12-28-2014

Re: Wait for external signal trigger in HLS block

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Hi,

I think a 'while loop' which polls for a signal is valid. When synthesized, it will simply translate into a FSM where one of the states will wait on the 'RX_aligned' signal to be asserted before transitioning to another state.

 

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1 Reply
Observer nikhilghanathe
Observer
340 Views
Registered: ‎12-28-2014

Re: Wait for external signal trigger in HLS block

Jump to solution

Hi,

I think a 'while loop' which polls for a signal is valid. When synthesized, it will simply translate into a FSM where one of the states will wait on the 'RX_aligned' signal to be asserted before transitioning to another state.

 

View solution in original post