12-07-2018 12:16 PM
I am not able to find a method to implement AXI full Slave interface using vivado HLS. Can someone suggest which pragmas/ directives ti use for implementing an AXI full Slave interface
12-11-2018 06:16 AM
As fare I know there is no way to realize a full AXI slave direct in HLS.
But if you want to adress big data, generate a BRAM interface from the HLS IP to the outside, attache an dual ported BRAM IP and on the other port attache a AXI master BRAM IP.
01-02-2019 08:03 AM
Actually I want to generate SystemC code for AXI Full Slave interface, and I thought it would be easier to generate it directly from the Vivado HLS. Can you suggest any other ways to generate system C code for the AXI full slave interface?
02-10-2019 09:54 AM
I just wanted to mention that HLS provides support for synthesizing SystemC code into RTL with the HLS tool. However, the HLS tool itself does not have the capability to produce any SystemC outputs. The ability to produce SystemC outputs is not on the roadmap, and will not be a part of the tool capabilities going forward. And I should probably also mention that using HLS to produce RTL to be used in a context outside of Vivado and Xilinx is forbidden in the licensing agreements of the tool.
OK, sorry HLS does not have the capability you are looking for with SystemC.
02-11-2019 03:26 AM
@rahul-vinus I'm pretty sure that HLS doesn't generate C/C++/SystemC code for any AXI interface. It just puts a tag in there that says "stick an AXI interface here" so the synthesis tool can insert an appropriate VHDL or Verilog implementation. As has been said above, it can't do a full AXI Slave anyway.