07-19-2019 06:42 AM
Please provide document and its link which is used to design FPGA using Vivado HLS 2019.1
07-19-2019 06:45 AM
HLS tutorial :
HLS user guide:
07-19-2019 11:51 AM
Please check the below Design hub page which has complete information with respect to HLS.
09-21-2019 10:42 PM
With reference to document ug871-vivado-high-level-synthesis-tutorial.pdf where I can find fir.c and related files?Which document I can find example C files that can be synthesizable? Any header files required for this?
If we are writing embedded software header files with all register initializations are generated by the tool itself based on the device selected. But if we are using C code for FPGA how that will be converted into synthesizable hardware?
I have worked earlier with VHDL and verilog for the ACTEL devices
Provide document link where in which I can drag and pull the blocks and design as per my requirement. Is it possible to generate equivalent vhdl or verilog or c file of the block?
I have downloaded vivado HLS 2019.1 webpack(free license) Please provide the details which works in this platform.
09-22-2019 04:13 AM
>> But if we are using C code for FPGA how that will be converted into synthesizable hardware?
Magic. Or, rather, HLS. That's exactly what HLS does. Xilinx is unlikely to explain exactly how HLS does it.
>> Provide document link where in which I can drag and pull the blocks and design as per my requirement
You can't do this in HLS. HLS is for converting C to hardware; and C is not a "drag and drop" sort of language. Once you've done the HLS side then you can drag and drop the resulting IP cores in Vivado's block diagram.
>> Is it possible to generate equivalent vhdl or verilog or c file of the block?
The C equivalent is trivial; you write the C code to make the HLS block, so the "C equivalent" is just the code you've already written. The HLS simulation just compiles that C code with GCC.
10-01-2019 03:59 AM
UG871 explains where you can find fir.c and the other design files on page 8:
Chapter 2, lab 1, step 4 tells you had to generate Verilog RTL, or how to change the language to your preferred choice: