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Explorer
Explorer
3,758 Views
Registered: ‎11-01-2015

Why are the results of interval in synthesis report not same as that in co-simulation report

Hi,

 

When I use Vivado HLS, I find the interval in synthesis report is not same as that in the co-simulation report.

 

This is the synthesis report. It shows the interval is 25.

s1.JPG

 

This is the co-simulation report. It shows the interval is 0.

s2.JPG

 

Attached is the source files.

 

Thanks,

Regards

 

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2 Replies
Xilinx Employee
Xilinx Employee
3,741 Views
Registered: ‎10-24-2013

Re: Why are the results of interval in synthesis report not same as that in co-simulation report

Hi @araongao2015

 

Please check the below link and see if that matches your use case.

https://www.xilinx.com/support/answers/60472.html

Thanks,Vijay
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Explorer
Explorer
3,728 Views
Registered: ‎11-01-2015

Re: Why are the results of interval in synthesis report not same as that in co-simulation report

Hi @vijayak

 

I read the message from the answer record you provided.

 

The II=111 from C/RTL co-simulation is calculated based on ap_start intervals (that is, how often new data is sent to the HLS module).

 

[Araon]: Does this mean the interval is measued using different method. In synthesis report, the II is the cycle between two adjacent ap_ready, while in cosimulation report, the II is the number of cycle between ap_start and the first ap_done. is this statement right?
  

The Vivado HLS C/RTL co-simulation testbench does not give data immediately after the HLS module is ready to accept data.
[Araon] Does this mean the mechanism among csim, C/RTL co-sim and RTL simulation is different?

When you use the IP in your own RTL, as soon as ap_ready is asserted, you can send new data to it to achieve II=28.
[Araon] So does this mean the cosimulation results are not reliable?
 
Thanks,
Regards
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