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chang.y.ab
Observer
Observer
7,378 Views
Registered: ‎02-26-2014

Why the HLS generates 2 port output interface?

Dear All:

 

I have a problem that the HLS generates 2 port output memory interface automaticlly.

Because the memory cannot be writen by 2 ports simultaneously,

I should prepare 2 memories for the ports and combine the data.

It is a strange process. How to avoid the 2 port memory output?

 

Best regards,

 

Yuyuan CHANG

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herver
Xilinx Employee
Xilinx Employee
7,376 Views
Registered: ‎08-17-2011

hello @chang.y.ab 

 

you can check the resource directive - use either pragma or tcl command but looks like you want to always do this so C pragma may be better.

 

***UG920 Chapter 4: High-Level Synthesis Reference Guide***

To specify which memory element in the library to use to implement an array, use the

set_directive_resource command. For example, this allows you to control whether

the array is implemented as a single or a dual-port RAM. This usage is important for arrays

on the top-level function interface, because the memory associated with the array

determines the ports in the RTL.

***

 

I HTH

 

- Hervé

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muzaffer
Teacher
Teacher
7,340 Views
Registered: ‎03-31-2012

Maybe you don't have to avoid 2 port memory? Xilinx FPGAs have what's called "true dual-port memory" feature where you have two completely separate ports through which you can do independent reads and writes, ie it's certainly possible to read from two different addresses at once.
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