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Visitor
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Registered: ‎09-24-2019

Write Convolutional Neural Network code in Vivado HLS or SDSoC?

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I have a trained neural network model written in Python and I am not sure what to do next.

I will have to somehow convert the code into C/C++ and then edit the code into HLS synthesizable code right?

 

So do I start converting the code into C/C++ using Visual Studio then SDSoc or Visual Studio then Vivado HLS?

 

Please help me as I am totally new to FPGAs.

(I am using a PYNQ Z-2 board)

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361 Views
Registered: ‎07-23-2019

Re: Write Convolutional Neural Network code in Vivado HLS or SDSoC?

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Some people launch a boat then decide where to go when in the middle of the sea. To be fair, I've done that as well. We are adventurous.

If you do ML on Python, I think the 'quickest' way is to use Pynq. It also accelerates functions on hardware so you get the FPGA at full steam.

I wouldn't add VisualStudio to the equation. 

If you want/ need to translate to C/C++ (I would avoid the latter, by the rule of "keep it simple"), that shouldn't be much of a problem, it's all normal Maths, algebra...

Now, between HLS and SDSoC, I would prefer the latter. SDSoC takes software and creates accelerated hardware for it. With HLS you would create your blocks in hardware as needed, then put them together and interface with software with AXI, etc. At the end, I think what's under the hood is that SDSoC 'encapsulates' HLS. Maybe SDSoC, for being 'higher' than HLS it's easier to miss things, but once over the learning curve, I think it's a leanest way.

 

PS: Oh, Dear... I just read "I'm totally new to FPGAs"

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Scholar u4223374
Scholar
375 Views
Registered: ‎04-26-2015

Re: Write Convolutional Neural Network code in Vivado HLS or SDSoC?

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If you do it with SDSoC, then the tools will help you to move parts of the design onto the FPGA while leaving other parts on the CPU. If you do it in HLS, it's all on the FPGA - the only code generated for the CPU is the drivers to start the block.

 

With that said, I'm pretty sure that there are a bunch of neural networks available for FPGAs and SoCs already - unless you really want the learning experience of writing your own, it's probably not worthwhile.

362 Views
Registered: ‎07-23-2019

Re: Write Convolutional Neural Network code in Vivado HLS or SDSoC?

Jump to solution

 

Some people launch a boat then decide where to go when in the middle of the sea. To be fair, I've done that as well. We are adventurous.

If you do ML on Python, I think the 'quickest' way is to use Pynq. It also accelerates functions on hardware so you get the FPGA at full steam.

I wouldn't add VisualStudio to the equation. 

If you want/ need to translate to C/C++ (I would avoid the latter, by the rule of "keep it simple"), that shouldn't be much of a problem, it's all normal Maths, algebra...

Now, between HLS and SDSoC, I would prefer the latter. SDSoC takes software and creates accelerated hardware for it. With HLS you would create your blocks in hardware as needed, then put them together and interface with software with AXI, etc. At the end, I think what's under the hood is that SDSoC 'encapsulates' HLS. Maybe SDSoC, for being 'higher' than HLS it's easier to miss things, but once over the learning curve, I think it's a leanest way.

 

PS: Oh, Dear... I just read "I'm totally new to FPGAs"

View solution in original post

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Visitor
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Registered: ‎09-24-2019

Re: Write Convolutional Neural Network code in Vivado HLS or SDSoC?

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Yeah, I feel quite lost in this world of FPGA. I am on this alone and it is quite intimidating. 

Thanks for your reply.

 

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265 Views
Registered: ‎07-23-2019

Re: Write Convolutional Neural Network code in Vivado HLS or SDSoC?

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You are brave. I've been using FPGA for about two decades and I still feel sometimes they come with more things I can keep up to, HLS, SDSoC... Unfortunately (or not), Xilinx has lately created a number of things that attract many only-software people and many crash like birds on a clean window. 

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