Showing results for 
Show  only  | Search instead for 
Did you mean: 
Registered: ‎03-29-2017

ZYNQ ULTRASCALE and MPSoc (ZCU111): Transfer the DATA from PL to PS


  I have written the Code (to generate HLS IP Block), and added that HLS IP to my Vivado design. I am trying to read the data (Look-up table data) from HLS IP and write to PS (Processor).

But i am unable to read the data (Look-up table data) properly. Please guide me. I have attached my design. Any wrong please correct me.



void FAPI_config(	uint8_t 	*mem_in,
					uint16_t 	*rnti,
					uint8_t 	*modulation,
					float 		*code_rate,
					uint8_t 	*RV,
					uint8_t 	*layers,
					uint8_t 	*N_PRB
//					uint8_t    	*resource_alloc_type,
//					uint8_t     *n_gap,
//					uint16_t    *preamble_index
#pragma HLS INTERFACE s_axilite port=return
#pragma HLS INTERFACE m_axi port= mem_in bundle= mem_in offset=slave
#pragma HLS INTERFACE ap_vld port=rnti
#pragma HLS INTERFACE ap_vld port=modulation
#pragma HLS INTERFACE ap_vld port=code_rate
#pragma HLS INTERFACE ap_vld port=RV
#pragma HLS INTERFACE ap_vld port=layers
#pragma HLS INTERFACE ap_vld port=N_PRB

	uint8_t config_data[584/8];

	memcpy((uint8_t *)config_data, (uint8_t *)(mem_in), 584/8);

	*modulation = modulation_table[MCS];

	*code_rate = code_rate_table[MCS]

	*rnti = config_data[DLSCH_Config_BASE+64/8];  //PDSCH

	*RV = config_data[DLSCH_Config_BASE+136/8];

	*layers = config_data[DLSCH_Config_BASE+168/8];

	*N_PRB = config_data[DLSCH_Config_BASE+224/8];



0 Kudos
1 Reply
Registered: ‎06-28-2018

Hi Thaus,

I have several questions, that may or may not have been arisen due to the fact that I don't know much about your design.

I'll give a few observations, maybe we can find what you are looking for.

The first thing that comes to mind, is that you want to read data on the PS side. However, I don't see any PL-to-PS connection of any of your output ports?

It seems that you want to load whatever content is given through mem_in into config_data. As a function of that, you have output ports that interpret something with the given data. You say that that data should come back to the PS but for now, you've only connected those outputs to the System ILA. Nothing else. A System ILA lives in the PL, so you've given no connection to the DDR of your ZCU, to read it back on the PS side (for example).

The System ILA should be able to see the data if the IP is initialized correctly; but only in the Hardware Manager of Vivado, not the Xilinx SDK! Since you have an ap_ctrl interface through the AXI-Lite bundle you've specified (s_axilite port=return), that means that your IP has to be: 

1) Initialized

2.1) If autorestart should be enabled, call AutoRestart from your HLS driver and then Start for it to loop forever.

2.2) If autorestart should be disabled, call DisableAutorestart from your HLS driver, and then Start for every transaction you want to perform.

If the IP is initialized correctly and you want a straight PL-to-PS connection, I would suggest putting ALL the interfaces into an Axilite bundle of the same name. You will see in the SDK that the inferred driver then contains all of your "variables". Now those would be registers of the same Axilite bus. You would then initialize, set the start/autorestart routine you like, and read back the results with the same driver whenever you feel like it.

If your IP should NOT have them all bundled into a single one Axilite bundle, because the output ports should say in the PL, I would suggest checking that the IP is initialized correctly and set into AutoRestart, for example. In this approach, the IP will constantly generate the output values given the contents of mem_in you have provided using the HLS driver.

I apologize if I have misinterpreted some things or not. Maybe you could clarify if I'm wrong, and we'll go from there!




edit: phrasing.

0 Kudos