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Explorer
Explorer
9,018 Views
Registered: ‎02-05-2008

ap_memory address when export to ip-catalog or edk

Hi

 

I have function with array argument. array size is 400. when I synthezise the report says the address is 9 bit. But when I export to ip-catalog or edk the address width shows 32 bit. Could you explain why?

 

Jothi

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Xilinx Employee
Xilinx Employee
9,017 Views
Registered: ‎07-11-2011

Hi

 

In general AXI address width is 32 please check if you have any AXI interface directives  to that addres

 

 

Regards,

Vanitha.

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Explorer
Explorer
9,012 Views
Registered: ‎02-05-2008

Hi
I do not gave any axi directive on this variable. Even I have checked with the example array_Ram. Still it gives 32 bit adders even the address is other number
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Xilinx Employee
Xilinx Employee
9,010 Views
Registered: ‎07-11-2011

Hi,

 

What is your addr data_type, can you show your code here ?

 

Regards,

Vanitha

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Explorer
Explorer
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Registered: ‎02-05-2008

Address data is not assigned by me. When you assign a directive ap_memory, depends on the array size, the address width is decided.

Jothi
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Xilinx Employee
Xilinx Employee
9,004 Views
Registered: ‎07-11-2011

Hi,

 

As synthesis shows 9 bit and only exporting makes difference I guess some interface directives were being added else it could be a tool issue.

Can you upload yoour test project for investigation ?

 

 

Regards,

Vanitha.

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Explorer
Explorer
9,002 Views
Registered: ‎02-05-2008

Hi

You could check the array_ram from the example design
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Explorer
Explorer
9,002 Views
Registered: ‎02-05-2008

I am using vivado 2013.3
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Moderator
Moderator
8,979 Views
Registered: ‎04-17-2011

Can see that but that's only external (32-bit) and on the top level wrapper of the generated IP to be added as the .bd in Vivado IPI. Internally its connected only to the 9 bits of ADDR respectively for the 3 ap_memory interfaces and rest of the bits are unused.
Regards,
Debraj
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Xilinx Employee
Xilinx Employee
8,974 Views
Registered: ‎11-28-2007

The packaged IP has 32-bit address bus. The actual memory depth is controlled by the MEM_SIZE (in bytes) property on the IP, which will be propagated to the BRAM connected to it in IPI.

 

 

Cheers,
Jim
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