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Explorer
Explorer
978 Views
Registered: ‎07-06-2016

axi master done bit for burst transfer (ZYNQ)

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Hello,

 

I'm trying to transfer an array of data from PL to PS (DDR). I saw many examples an posts and I already implemented in HLS the code to do it. I've got a control axi lite for the axi master where I can setup from SDK the memory address to write to, but I haven't seen any reference on how to indicate the burst transfer is done... 

 

I'd like to tell to the PS that the data is already transferred and is ready to read, how would be the best way to do it?

 

Thanks.

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1,292 Views
Registered: ‎03-27-2014

Re: axi master done bit for burst transfer (ZYNQ)

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@joseer wrote:

 

Do you know how to generate that interrupt from the HLS IP? 


add an extra output bit to your current logic and determine when it should be asserted (end of transfer condition).

 

then in a block design, connect this bit to the Zynq IRQ lines and look for IRQ based examples in the Vivado SDK to figure how to trigger the receiver

G.W.,
NIST - Time Frequency metrology
3 Replies
976 Views
Registered: ‎03-27-2014

Re: axi master done bit for burst transfer (ZYNQ)

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@joseer wrote:

 

I'd like to tell to the PS that the data is already transferred and is ready to read, how would be the best way to do it?

 


I would rather use an interrupt signal (IRQ) but in a Linux context that might be a little more complicated if you have never done it before. You need to declare the IRQ and associated methods in the kernel (device driver), and you will need some sort of mechanism like irq_wait_interruptible()+spin lock to wait for the IRQ to actually happen and so, make data available. There are many approaches and ways to do that, semaphore+counters could be another way to do that.

G.W.,
NIST - Time Frequency metrology
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Explorer
Explorer
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Registered: ‎07-06-2016

Re: axi master done bit for burst transfer (ZYNQ)

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Hi @guillaumebres, thanks for the reply, I forgot to say but is for a bare metal application no linux. 

 

Do you know how to generate that interrupt from the HLS IP? 

 

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1,293 Views
Registered: ‎03-27-2014

Re: axi master done bit for burst transfer (ZYNQ)

Jump to solution

@joseer wrote:

 

Do you know how to generate that interrupt from the HLS IP? 


add an extra output bit to your current logic and determine when it should be asserted (end of transfer condition).

 

then in a block design, connect this bit to the Zynq IRQ lines and look for IRQ based examples in the Vivado SDK to figure how to trigger the receiver

G.W.,
NIST - Time Frequency metrology