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Adventurer
Adventurer
683 Views
Registered: ‎03-15-2012

axi4 lite clock/reset

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hi,

i try to create a HLS module with an axi4lite interface for parameters but controllable via hardware. So i used the following:

 

#pragma HLS INTERFACE ap_ctrl_hs port=return
#pragma HLS INTERFACE s_axilite port=p_coeff,centerx,centery,matrix0,matrix1,matrix2,matrix3,matrix4,matrix5,baseAddrA,baseAddrB,busy

But the module reset was not how i needed it. The module should be resettable by any time, but the axilite interface was conntected too, so the interface could got stuck, when a reset occured during a transfer.

 

What i need is one reset for axilite and one for the module itself.

So i tried:

 

#pragma HLS INTERFACE ap_ctrl_hs port=return
#pragma HLS INTERFACE s_axilite port=p_coeff,centerx,centery,matrix0,matrix1,matrix2,matrix3,matrix4,matrix5,baseAddrA,baseAddrB,busy clock=a4l_clk

to get it right, but now the clocks and resets seems to be mixed. In Module the axi4lite submodule is connected like this:

 

 

        ACLK => ap_clk,
        ARESET => ap_rst_n_inv,
...
        clk => a4l_clk,
        rst => ap_rst_n_a4l_clk_inv);

But in the submodule:

    -- read FSM
    process (clk)
    begin
        if (clk'event and clk = '1') then
            if (ARESET = '1') then
                rstate <= rdidle;
            elsif (ACLK_EN = '1') then
                rstate <= rnext;
            end if;
        end if;
    end process;
...
    process (ACLK)
    begin
        if (ACLK'event and ACLK = '1') then
            if (rst = '1') then
                int_busy_V_ap_vld <= '0';
            elsif (ACLK_EN = '1') then
                if (busy_V_ap_vld = '1') then
                    int_busy_V_ap_vld <= '1';
                elsif (busy_V_vld_get = '0' and busy_V_vld_ext = '1') then
                    int_busy_V_ap_vld <= '0'; -- clear on read
                end if;
            end if;
        end if;
    end process;

It seems, the synchronous resets have a CDC and the axi4lite interface will be resetted by the module and some module register will be resetted by the axi4lite reset.

Did i do something wrong?

How do i get 2 resets, one for axi4lite interface (and only for that) and one for the module (without resetting the interface)?

 

thanks

 

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Moderator
Moderator
614 Views
Registered: ‎10-04-2011

Re: axi4 lite clock/reset

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Hello @dm78,

Unfortunately, the HLS tool does not yet have the ability to manage different reset domains for the interface protocols and the internal logic. I spoke with the marketing and engineering teams about this and they are aware of the need to add this capability and understand this use case. OK, sorry we do not have the ability you were looking for here.

Regards,
Scott 

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2 Replies
Moderator
Moderator
615 Views
Registered: ‎10-04-2011

Re: axi4 lite clock/reset

Jump to solution

Hello @dm78,

Unfortunately, the HLS tool does not yet have the ability to manage different reset domains for the interface protocols and the internal logic. I spoke with the marketing and engineering teams about this and they are aware of the need to add this capability and understand this use case. OK, sorry we do not have the ability you were looking for here.

Regards,
Scott 

View solution in original post

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Adventurer
Adventurer
594 Views
Registered: ‎03-15-2012

Re: axi4 lite clock/reset

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Hi and thanks for the answer.

With other words, generally using different clocks for different Interfaces is possible but limited and has to be verified very carefully e.g. by reverse engineering.

Btw, i solved my problem by using my own axi4lite interface module.