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satvik9999
Participant
Participant
10,271 Views
Registered: ‎09-13-2015

clock event in vivado HLS

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hello all,

 

While i generate Verilog from c code in vivado HLS i found few input and output generated by default(i.e ap_clk,ap_rst,ap_done etc.). While i serch about it i read that software generated by default.

 

So my question is that Can i disable that in vivado HLS? so vivado HLS can not generate those input output by default in verilog file.

 

second question is that if i can not disable that by default input output so can i use ap_clk(a hardwear clock) in my c language code because i want to do work on negative edge of clock(ap_clock) in my c language code.

 

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fanat9
Explorer
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19,248 Views
Registered: ‎02-16-2014

Insert directive AP_CTRL_NONE.

 

 

#pragma HLS INTERFACE ap_ctrl_none port=return

 

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fanat9
Explorer
Explorer
19,249 Views
Registered: ‎02-16-2014

Insert directive AP_CTRL_NONE.

 

 

#pragma HLS INTERFACE ap_ctrl_none port=return

 

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satvik9999
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10,242 Views
Registered: ‎09-13-2015

thank you so much for reply 

 

But when i make a tricky program in which i call a function inside a function(module instance into top module according to verilog) then i got error with ap_ctrl_none, without that directive mode my programs run sucessfully.

i atteched my code and error message screenshot into attachments.

 

kindly please solve my problem.

 

Thank you in advance.

 

prgram_c1_and_c2.PNG
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fanat9
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Explorer
10,231 Views
Registered: ‎02-16-2014

This directive can only be applied to top level function. There is no need to set it to subroutines.

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satvik9999
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Registered: ‎09-13-2015
Thank you fanat9 for reply

i applied that in only top level function then also i got error.
I did not apply it on subroutines.

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jesko
Adventurer
Adventurer
10,131 Views
Registered: ‎09-25-2015

looks to me that your design needs the interface because you return a value (in the main function) ...

 

I have difficulties to imagine a disgn with no interfaces ... self generating input and waste output ?

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