clock event in vivado HLS

[satvik9999]

hello all,

While i generate Verilog from c code in vivado HLS i found few input and output generated by default(i.e ap_clk,ap_rst,ap_done etc.). While i serch about it i read that software generated by default.

So my question is that Can i disable that in vivado HLS? so vivado HLS can not generate those input output by default in verilog file.

second question is that if i can not disable that by default input output so can i use ap_clk(a hardwear clock) in my c language code because i want to do work on negative edge of clock(ap_clock) in my c language code.

[fanat9 · Accepted solution]

Insert directive AP_CTRL_NONE.

#pragma HLS INTERFACE ap_ctrl_none port=return

[satvik9999]

thank you so much for reply fanat9 

i used ap_ctrl_none mode and in simple programs like a single function program in which i made led on and of according to switch and i got sucess to disable by default generated ports.

But when i make a tricky program in which i call a function inside a function(module instance into top module according to verilog) then i got error with ap_ctrl_none, without that directive mode my programs run sucessfully.

i atteched my code and error message screenshot into attachments.

kindly please solve my problem.

Thank you in advance.

[fanat9]

This directive can only be applied to top level function. There is no need to set it to subroutines.

[satvik9999]

Thank you fanat9 for reply

i applied that in only top level function then also i got error.
I did not apply it on subroutines.

[jesko]

looks to me that your design needs the interface because you return a value (in the main function) ...

I have difficulties to imagine a disgn with no interfaces ... self generating input and waste output ?