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ayush_joshi
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Registered: ‎04-06-2017

connecting two ap_fifo ports together

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Hello all

 

I am having a bit of trouble connecting two ips which I generated in HLS.

As shown in figure attached, IP trigger_0 has an output port [ap_fifo] which has to be connected to the input [ap_fifoport  an IP algo_0 . 

But as I am trying to connect the two, vivado is unable to detect any matching ports for the connection [as can be seen from figure].

How can I possibly connect the two? 

[Note that I do not want to use axis interface for connection as in that case I am having troubles in data-packing the two ports (apparently because of some interference with HLS stream classes I used) in discussion] 

 

- A.Joshi

 

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lematthias
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Registered: ‎09-15-2018

Hi,
the FIFO pragma only creates the FIFO interface inside the HLS IP. You will have to attach the port to a FIFO in your block design. The 'depth' value is only for C-Simulation (same for aximm ports).

HLS pragmas are explained in UG902 and you can find a summary here:
https://www.xilinx.com/html_docs/xilinx2019_1/sdaccel_doc/hls-pragmas-okr1504034364623.html#jit1504034365862

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lematthias
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Registered: ‎09-15-2018

Hi
It would be nice to know if you ever found a solution as I am interested in this as well.
Thanks!

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lematthias
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1,648 Views
Registered: ‎09-15-2018

Using the interface ap_fifo in Vivado HLS only generates the interface but not the FIFO itself.

Vivado 2018.2 comes with the "FIFO Generator" IP which can be used for this. Manually add it to the block design and put it in between the two HLS IPs. Unfortunately the connection automation in 2018.2 doesn't seem to be able to handle these ports, so they need to be connected by hand.

Good luck

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mbence76
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Explorer
799 Views
Registered: ‎01-18-2019

Hi Matthias,

I have the same question as the poster did years ago.  I was thinking maybe the FIFOs themselves are not generated by Vitis HLS, but why is Vitis HLS offering pragmas to set the depth of the FIFO?  Or this has changed since April 2019?

Thank you

Miklos

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blank
Visitor
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735 Views
Registered: ‎10-30-2020

You have to put a fifo between the two interfaces, I think.

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mbence76
Explorer
Explorer
724 Views
Registered: ‎01-18-2019

Yes, it looks like that.

But in that case I will have 1 FIFO in one IP,  1 FIFO in another IP and 1 FIFO in between.  That does not really make sense. Apparently one IP is supposed to have a different interface, not a FIFO.

Miklos

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blank
Visitor
Visitor
713 Views
Registered: ‎10-30-2020

There won't be a FIFO in each IP. It only generates a FIFO interface instead of FIFO itself.

lematthias
Participant
Participant
707 Views
Registered: ‎09-15-2018

Hi,
the FIFO pragma only creates the FIFO interface inside the HLS IP. You will have to attach the port to a FIFO in your block design. The 'depth' value is only for C-Simulation (same for aximm ports).

HLS pragmas are explained in UG902 and you can find a summary here:
https://www.xilinx.com/html_docs/xilinx2019_1/sdaccel_doc/hls-pragmas-okr1504034364623.html#jit1504034365862

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mbence76
Explorer
Explorer
706 Views
Registered: ‎01-18-2019

You are right.

Now I re-read ug902 and what I missed was that although you can set the FIFO size, this applies for streams in between C functions only. It does not apply to stream on the top level interfacing the outside world.

Question solved, thank you!

Miklos

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mbence76
Explorer
Explorer
482 Views
Registered: ‎01-18-2019

One more thing worth to know:   Vitis HLS  seems to expect  fall-thru FIFOs by default !

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