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derickshi
Adventurer
Adventurer
2,820 Views
Registered: ‎11-25-2015

error when running C/RTL co-simulation

Hello guys,

 

I'm studying HLS, I designed a simple module which is a floating point accumulator. I encountered this error when I was running C/RTL co-simulation:

 

ERROR: [XSIM 43-3238] Failed to link the design.
ERROR: Please check the snapshot name which is created during 'xelab',the current snapshot name "xsim.dir/accum/xsimk.exe" does not exist

 

It didn't happen when I run co-simulation for the tutorial designs. My design passed the simulation and synthesis program didn't report any errors.  So I think there is something wrong with my code:

 

DUT:

#include <iostream>
#include "accum.h"

using namespace std;

double accum(double input[100]){
	double output = 0;
	accum_label0:for (int i=0;i<100;i++){
		output = output + input[i];
	}
	return output;
}

Testbench:

#include "accum.h"
#include <iostream>

using namespace std;

int main(){
	double input[100];
    double output_sw=0;
    double output_hw;
    for(int i=0;i<100;i++){
    	input[i] = i;
    }
    for(int i=0;i<100;i++){
    	output_sw=output_sw+input[i];
    }

    output_hw = accum(input);

    cout<<"the software result:"<<output_sw<<"\n";

    cout<<"the hardware result:"<<output_hw<<"\n";

    if(output_sw==output_hw){
    	cout<<"compare success!"<<"\n";
    	return 0;
    }
    else if(output_sw!=output_hw){
    	cout<<"compare failed!"<<"\n";
    	return 1;
    }
}

I'm really confused about it.

Thanks in advance,

 

Derick

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3 Replies
muzaffer
Teacher
Teacher
2,809 Views
Registered: ‎03-31-2012

@derickshi I ran your system with the following script and I had no problems with cosim. What OS and Vivado version are you using?

 

open_project -reset accum
set_top accum
add_files dut.cpp -cflags "-DFIXED"
add_files -tb tb.cpp -cflags "-I/opt/Xilinx/Vivado_HLS/2015.4/include -std=c++0x"
open_solution -reset "solution1"
#set_part {xc7z045iffv900-2l}                                                                                                                                                                                                                                     
#set_part kintexu
#set_part xc7z020iclg400-1l
set_part xc7z020clg400-2
#set_part xc7z030sbv485-2
#set_part {xcku040-fbva900-2-e}
#set_part {xcku040-sfva784-1-c}
create_clock -period 5 -name default
#source "directives.tcl"
#csim_design
csynth_design
cosim_design
#export_design -evaluate verilog -format ip_catalog
export_design -format ip_catalog
exit
- Please mark the Answer as "Accept as solution" if information provided is helpful.
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derickshi
Adventurer
Adventurer
2,802 Views
Registered: ‎11-25-2015

@muzaffer thanks for the reply. My OS is windows 7 and I'm using Vivado HLS 2016.2.

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derickshi
Adventurer
Adventurer
2,797 Views
Registered: ‎11-25-2015

@muzaffer

 

After I removed the loop unroll directive for the loop, the errors are just gone. Is it because the loop in my code has data dependency so it can't be unrolled?

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