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Observer liujiawei_0308
Observer
533 Views
Registered: ‎09-16-2019

hls::qr_inverse

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I'm trying to run C-synthesis for the given example hls::qr_inverse in Vivado HLS. After completing the synthesis, I found that the clock period did not meet the requirement

The warning message is "WARNING: [SCHED 204-21] Estimated clock period (4.223ns) exceeds the target (target clock period: 4ns, clock uncertainty:
0.5ns, effective delay budget: 3.5ns). "

How should I make the clock period meet the requirements?

 

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1 Solution

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Moderator
Moderator
333 Views
Registered: ‎05-31-2017

Re: hls::qr_inverse

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@liujiawei_0308 ,

Ideally Vivado HLS uses the “Specified clock period – clock uncertainty”  as a clock period for Vivado HLS synthesis. This is to provide a margin for any delays during the place and route.

If we don’t specify any uncertainty by default Vivado HLS takes uncertainty as 12.5% of the specified clock period.

 

You need not worry until the Clock Period achieved after post-Implementation is less than the specified Clock Period.

View solution in original post

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6 Replies
Moderator
Moderator
473 Views
Registered: ‎05-31-2017

Re: hls::qr_inverse

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Hi @liujiawei_0308 ,

I would suggest you export the RTL and run through synthesis and place and route.  The clock period from HLS after synthesi is just an estimate. Place & Route will give you the real numbers.

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Moderator
Moderator
403 Views
Registered: ‎11-21-2018

Re: hls::qr_inverse

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Hi @liujiawei_0308 

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply).

 

If this is not solved/answered, please reply in the topic giving more information on your current status.

 

Thanks and Regards,

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Observer liujiawei_0308
Observer
363 Views
Registered: ‎09-16-2019

Re: hls::qr_inverse

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Hi @shameera 

After outputting RTL, I looked at the report file in the solution1\syn directory and found that the clock cycles of matrix_multiply_alt2_csynth. rpt and qr_inverse_top_csynth. rpt files were still not up to the requirements. I would like to ask how Place&Route are implemented in HLS. I just learned HLS, many operations are not very familiar with it.

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Moderator
Moderator
359 Views
Registered: ‎05-31-2017

Re: hls::qr_inverse

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@liujiawei_0308 ,

Vivado HLS just converts the written high level language in to the HDL.

At the back of Vivado HLS if we select synthesis / Place & Route, HLS calls vivado at the backend and runs placement and routing on the generated HDL.

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Observer liujiawei_0308
Observer
342 Views
Registered: ‎09-16-2019

Re: hls::qr_inverse

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Hi @shameera 

When exporting RTL, I select "vivado synthesis,place and route".After export, the report displays

#=== Final timing ===
CP required: 4.000
CP achieved post-synthesis: 3.173
CP achieved post-implementation: 3.809
Timing met

Does this mean that the design meets the timing requirements?

My uncertainty is 0.50,but final clock period is 3.809 higher than 3.50. May I ask if there will be any mistake?

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Moderator
Moderator
334 Views
Registered: ‎05-31-2017

Re: hls::qr_inverse

Jump to solution

@liujiawei_0308 ,

Ideally Vivado HLS uses the “Specified clock period – clock uncertainty”  as a clock period for Vivado HLS synthesis. This is to provide a margin for any delays during the place and route.

If we don’t specify any uncertainty by default Vivado HLS takes uncertainty as 12.5% of the specified clock period.

 

You need not worry until the Clock Period achieved after post-Implementation is less than the specified Clock Period.

View solution in original post

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