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Explorer
Explorer
6,930 Views
Registered: ‎10-09-2014

problem with ap_none signal input with 2015.3

Hi, 

 

I notice that 2015.3 is handling ap_none input in a weird way compared to 2015.1. I have created a simple design to reproduce the problem as attached. I have a top level function as: 

 

void test(ap_uint<8> sts, hls::stream<axiWord>& in, hls::stream<axiWord>& out) {

static hls::stream<axiWord> temp;
moveToFifo<0>(in, temp);
moveToFifoTmp(sts, temp, out);
}

 

It has one stream input and one ap_none data input, the only comsumer of the input fifo is a function called moveToFifo as followed:

 

template <int tag, typename T>
void moveToFifo(hls::stream<T>& in, hls::stream<T>& out) {
if (!in.empty() && !out.full()) {
out.write(in.read());
}
}

 

However, from the verilog code it generated as followed, you can see that the sts signal is somehow included into the moveFifo function and got converted into a fifo interface. So now the ready signal for the moveToFifo is dependent to the downstream consumer of the sts_channel. If it somehow stucks when writing to a full fifo, it will keep back pressure to this function and stop it from reading from the data input. I have a design that was working in 2015.1 but now freezes when I send data in a higher rate. 

 

 

module test_moveToFifo_0_axiWord_51 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
in_TDATA,
in_TVALID,
in_TREADY,
in_TKEEP,
in_TLAST,
sts_V,
sts_V_out_din,
sts_V_out_full_n,
sts_V_out_write,
temp_V_data_V_din,
temp_V_data_V_full_n,
temp_V_data_V_write,
temp_V_keep_V_din,
temp_V_keep_V_full_n,
temp_V_keep_V_write,
temp_V_last_V_din,
temp_V_last_V_full_n,
temp_V_last_V_write
);

 

Thanks,

Jimmy

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4 Replies
Observer dasidler
Observer
1,128 Views
Registered: ‎04-23-2014

Re: problem with ap_none signal input with 2015.3

@linzhongduo were you able to find a workaround for this problem?
I have a very similar issue in 2018.1.

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Explorer
Explorer
1,118 Views
Registered: ‎10-09-2014

Re: problem with ap_none signal input with 2015.3

No, Xilinx just updated the HLS user guide that this is not supported.... I do not think they will work on this. If you can contact a field support, they might be able to fire a ticket to the dev team.

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Highlighted
Observer dasidler
Observer
1,109 Views
Registered: ‎04-23-2014

Re: problem with ap_none signal input with 2015.3

@linzhongduo thanks for the fast reply.

To me the ap_none documentation is not very clear, i see that his requirements were added from 2015.1 to 2015.3:


the ap_none interface does requires the following:

  • Producer blocks to do one of the following:
    • Provide data to the input port at the correct time
    • Hold data for the length of a transaction until the design completes
  • Consumer blocks to read output ports at the correct time

Frankly, i don't understand why they removed this very simply feature. I am wondering if the best practice is to pass these input arguments with a stream as well.

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Explorer
Explorer
1,104 Views
Registered: ‎10-09-2014

Re: problem with ap_none signal input with 2015.3

cannot comment on this. I have been waiting for years for Xilinx to fix this problem or provide a guideline of best practice. For me, all the problematic inputs are only for initialisation, so whatever bug they are trying to solve in 2015.3 shouldn't affect this simple case.
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