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lmaxeniro
Explorer
Explorer
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Registered: ‎09-09-2019

question regarding HLS m_axi and s_axilite configuration

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Dear all,

Some question please anyone can help, take the example as below (which come from the example proj https://github.com/Xilinx/BNN-PYNQ/blob/master/bnn/src/network/cnvW1A1/hw/top.cpp # 194)

questions:

1. why m_axi port (in/out) have the s_axilite property be assigned? i.e. the in/out port are defined both axi and axi lite--that sounds not right??

2. about bundle option: "bundle" from the document is used for "tied to" the port to the specified bus (bundle="bus name") or the global memory (gmem)? is that correct? but what name has to be used? in this example, bundle= hostmem, "hostname" needs to be something defined specifically in the design somwhere?

3. in HLS documentation, on m_axi definition about the offset=salve option, it is mentioned "slave: Adds a 32-bit register inside the AXI4-Lite interface for applying an address offset." that back refer to the question1, which means a AXI port (m_axi), if have have offest=slave assigned, will also be a AXI-lite port???

 

 

void BlackBoxJam(ap_uint<64> *in, ap_uint<64> *out, bool doInit,
		unsigned int targetLayer, unsigned int targetMem,
		unsigned int targetInd, unsigned int targetThresh, ap_uint<64> val, unsigned int numReps) {
// pragmas for MLBP jam interface
// signals to be mapped to the AXI Lite slave port
#pragma HLS INTERFACE s_axilite port=return bundle=control
...
#pragma HLS INTERFACE s_axilite port=val bundle=control
#pragma HLS INTERFACE s_axilite port=numReps bundle=control
// signals to be mapped to the AXI master port (hostmem)
#pragma HLS INTERFACE m_axi offset=slave port=in bundle=hostmem depth=512
#pragma HLS INTERFACE s_axilite port=in bundle=control
#pragma HLS INTERFACE m_axi offset=slave port=out bundle=hostmem depth=16
#pragma HLS INTERFACE s_axilite port=out bundle=control

 

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randyh
Xilinx Employee
Xilinx Employee
257 Views
Registered: ‎01-04-2013

Hello, I would suggest you read this section on Interface Synthesis to answer some of your questions. 

1. There are actually multiple signals that are associated with the interface, each of these signals would be use a port. The data channels, address, the control protocols, all grouped together to define the interface. The s_axilite interface and the m_axi interface are two different collections of ports, but they both serve the data transfer associated with the m_axi port. The s_axilite has control registers that are associated with the operation of the kernel and the transfer of data from the host to the kernel. 

https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/managing_interface_synthesis.html#cjd1615753986931

2. There are two interfaces but neither is going to be named "in", though the m_axi port should have some ports associated with the "in" argument. The API is dealing with the needed interfaces for a specific transaction. In the host application you are identifying the kernel and kernel arguments, and these are associated with the interfaces. 

3. the bundle groups the arguments into a single m_axi interface or multiple m_axi interfaces. gmem (for global memory) is just a portion of the name given to the interface. If you specify a single bundle then arguments "in1" and "in2" for example are grouped into a single AXI interface called m_axi_gmem or m_axi_bundle, or whatever you called your bundle. If you specify separate bundles, then "in1" would be assigned to m_axi_gmem0 and "in2" would be assigned to m_axi_gmem1. The two m_axi interfaces would consume extra resources but provide greater flexibility for data transfer. 

4. The address offset is managed by the Xilinx Runtime (XRT) or by you and software drivers. 

 

 

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randyh
Xilinx Employee
Xilinx Employee
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Registered: ‎01-04-2013

You can refer to the documentation for the details you are looking for: 

https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/managing_interface_synthesis.html#qoa1585574520885

The s_axilite provides an address offset to the m_axi port that is used when transferring data into the kernel. The s_axilite also provides a variety of other services, but this is why the s_axilite is associated with the m_axi interface. In the Vitis environment, the offset is always slave. With regard to your question 3, it is the same s_axilite interface that provides these services. The Vitis kernel flow supports only one s_axilite interface. 

The bundle lets you group ports into a single interface, or create multiple interfaces that can be assigned to different memory banks to improve performance. The name is user-definable, and defaults to gmem, which results in an integrated name like m_axi_gmem0. If you bundle everything into one bus interface, that reduces the resources required to implement the interface but may limit your performance due to reads/writes. You can specify multiple bundles to improve performance but increase resource usage. 

When you use the kernel in a design to build the device binary (xclbin) in the Vitis tool you can assign the different bundles to specific memory resources, or let XRT manage that for you. 

https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/buildingdevicebinary.html#ejl1524519365386

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lmaxeniro
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Registered: ‎09-09-2019

@randyh Thanks a lot for the reply, that is much clear for me, but still some confusion could you help to clarify:

1. From my understanding a physical port, can not be both axi and the axi-lite, that is a fundamental confusing point for me.. please correct me if I am wrong?

Also please help to check and correct my understanding are correct or not (they are all based on Q1's answer):

2. May I say that for the above example, there exist two physical ports, both name are "in" but one is attached with the axi bus, another attached to axi-lite bus, and the "in" axi-lite bus is associate with the "in" axi for the controlling purpose. Actually when I write a Host program to use the port "in" (for exp, using openCL API enqueueWriteBuffer/enqueueReadBuffer) --the hw are dealing both two interfaces..

3. bundle option tells the hls that what above physical port be connected to internally (global mem is gmem - some code I see gmem0, are they same? for different mem bank for a SSI board for exp U200, need to be assigned out of the hls--as your 2nd link indicate).

4. with the offset=slave setup (only meaningful when an associate axi-lite interface exist) , the HW address offset is managed by HLS, or axi C driver? --as there is nothing about address offset mentioned explicitly.

 

Thanks again for your help..

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randyh
Xilinx Employee
Xilinx Employee
258 Views
Registered: ‎01-04-2013

Hello, I would suggest you read this section on Interface Synthesis to answer some of your questions. 

1. There are actually multiple signals that are associated with the interface, each of these signals would be use a port. The data channels, address, the control protocols, all grouped together to define the interface. The s_axilite interface and the m_axi interface are two different collections of ports, but they both serve the data transfer associated with the m_axi port. The s_axilite has control registers that are associated with the operation of the kernel and the transfer of data from the host to the kernel. 

https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/managing_interface_synthesis.html#cjd1615753986931

2. There are two interfaces but neither is going to be named "in", though the m_axi port should have some ports associated with the "in" argument. The API is dealing with the needed interfaces for a specific transaction. In the host application you are identifying the kernel and kernel arguments, and these are associated with the interfaces. 

3. the bundle groups the arguments into a single m_axi interface or multiple m_axi interfaces. gmem (for global memory) is just a portion of the name given to the interface. If you specify a single bundle then arguments "in1" and "in2" for example are grouped into a single AXI interface called m_axi_gmem or m_axi_bundle, or whatever you called your bundle. If you specify separate bundles, then "in1" would be assigned to m_axi_gmem0 and "in2" would be assigned to m_axi_gmem1. The two m_axi interfaces would consume extra resources but provide greater flexibility for data transfer. 

4. The address offset is managed by the Xilinx Runtime (XRT) or by you and software drivers. 

 

 

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