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yihaohuang0112
Visitor
Visitor
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Registered: ‎09-26-2020

recipe for target "nnet.o" failed without errors

I am trying to do C simulation with a testbench, I have already finished the synthesis part without error but C simulation failed. The attached part is the Error message I get, but I did not find any fatal error in the code, only this warning, Could you please help me with that? Thanks!

 

 

INFO: [SIM 211-4] CSIM will launch GCC as the compiler.
Compiling ../../../../nnet.cpp in debug mode
csim.mk:80: recipe for target 'obj/nnet.o' failed
In file included from C:/Xilinx/Vivado/2019.2/include/floating_point_v7_0_bitacc_cmodel.h:143:0,
from C:/Xilinx/Vivado/2019.2/include/hls_fpo.h:186,
from C:/Xilinx/Vivado/2019.2/include/hls_half.h:44,
from C:/Xilinx/Vivado/2019.2/include/etc/ap_private.h:90,
from C:/Xilinx/Vivado/2019.2/include/ap_common.h:641,
from C:/Xilinx/Vivado/2019.2/include/ap_fixed.h:54,
from ../../../../weights.h:23,
from ../../../../nnet.cpp:22:
C:/Xilinx/Vivado/2019.2/include/gmp.h:62:0: warning: "__GMP_LIBGMP_DLL" redefined
#define __GMP_LIBGMP_DLL 0

In file included from C:/Xilinx/Vivado/2019.2/include/hls_fpo.h:186:0,
from C:/Xilinx/Vivado/2019.2/include/hls_half.h:44,
from C:/Xilinx/Vivado/2019.2/include/etc/ap_private.h:90,
from C:/Xilinx/Vivado/2019.2/include/ap_common.h:641,
from C:/Xilinx/Vivado/2019.2/include/ap_fixed.h:54,
from ../../../../weights.h:23,
from ../../../../nnet.cpp:22:
C:/Xilinx/Vivado/2019.2/include/floating_point_v7_0_bitacc_cmodel.h:135:0: note: this is the location of the previous definition
#define __GMP_LIBGMP_DLL 1

make: *** [obj/nnet.o] Error 1
ERROR: [SIM 211-100] CSim file generation failed: compilation error(s).
INFO: [SIM 211-3] *************** CSIM finish ***************

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3 Replies
aoifem
Moderator
Moderator
554 Views
Registered: ‎11-21-2018

Hi @yihaohuang0112 

 

The community has seen issues like this in the past. Can you see if the following posts solve your issue? : 

https://forums.xilinx.com/t5/High-Level-Synthesis-HLS/Something-Wrong-When-Including-Fixed-Point-Header-File/td-p/1001037

https://forums.xilinx.com/t5/High-Level-Synthesis-HLS/Run-C-RTL-co-simulation-failed/td-p/675109

 

 

 

 

 

 

 

 

Aoife
Product Application Engineer - Xilinx Technical Support EMEA


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0 Kudos
268 Views
Registered: ‎02-20-2020

 .@yihaohuang0112   can you find the solution.

 I am facing the same problem., but couldn't find any solution from the links that were listed above.

I just can not understand what exactly is the problem in my code.

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yihaohuang0112
Visitor
Visitor
210 Views
Registered: ‎09-26-2020

I think this is really tricky... its definitely something wrong in the code file before that "error in linking", sometimes I include some files twice and sometimes I just remove that file, and it works

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