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Registered: ‎10-06-2017

regarding programming control registers of IP through AXI Lite


We have designed an IP block with AXILite interface to access control/status registers. The IP has a control register with IP enable
bit. Only when IP enable is 1, the IP starts accepting data on its input interface and processes it. So first we configure the IP by
writing the appropriate values of control registers and then make IP enable bit 1 to enable the operation.
During the functional testing, we are first making the IP enable bit zero ,then calling an Init function which initialises all the
registers with proper values and then we make IP enable bit 1.
Since we are making the IP enable bit 0 followed by 1, the C compiler seems to optimise it and directly sets the value to 1.So in C RTL co-simulation, we see value of only 1. Ideally it should be set to 0 then initialisation on AXI Lite of all control registers and then IP Enable bit set to 1.

How can we acheive this sequence?

Awaiting reply,



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3 Replies
Registered: ‎06-28-2018

Hello Mahesh,

I would guess that the register itself is initialized to 0 and then written on with a 1? Since I don't know what is exactly in between both operations, I will venture myself and tell you to try an ap_wait() statement in between both.

For verification purposes, you can even put more than one ap_wait() in between both actions. Something like:

ap_uint<32> ctrl_reg = 0x0000;

// Init phase

for (int i = 0; i < init_delay; i++) {



ctrl_reg |= (1 << 1); 


If this is the problem you're having, you should see ctrl_reg going from 0 to 1 in a init_delay amount of time in cycles.




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Registered: ‎10-06-2017

Thanks Julian for your inputs.

We tried the following code:

typedef struct


ap_uint<1> ip_enable;

ap_uint<1> global_intrpt_enable;



fun(control_register ctrl_reg)


#pragma HLS INTERFACE s_axilite port=ctrl_reg

ctrl_reg.ip_enable = 0;

for(int i=0;i<5;i++)




ctrl_reg.ip_enable = 1;




We do not see the setting of ctrl_reg.ip_enable after delay. What could be the reason? How do we get over it?

The control_reg is accessible through AXI_Lite interface. We are also resetting it to zero using config_rtl command to reset it to zero. 

After reset, ctrl_reg.ip_enable should be zero and after a delay (after write on AXI_Lite) it should go to  1. 

But we are seeing a continuous value of 1 on control_reg.ip_enable. It is 1 right from t=0.

please guide,




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Registered: ‎04-26-2015 

Try changing the function definition to this:


fun(volatile control_register ctrl_reg)

"volatile" in C essentially means "it is not safe to assume that this process is the only one accessing this data, so no optimization of access to this data is acceptable".

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