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Observer bva_rzn
Observer
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Registered: ‎07-04-2017

start hls ip block with an axi master in vivado

Hello.

The question is how to start the hls module in vivado.
Test module code:

void AXI_burst(u64 aIn[32],hls::stream<u64stream> &aOut)

{

   #pragma HLS INTERFACE ap_ctrl_hs port=return

   #pragma HLS INTERFACE axis port=aOut

   #pragma HLS INTERFACE m_axi depth=32 port=aIn offset=off max_read_burst_length=32

   #pragma HLS STREAM depth=32 variable=aOut

 

   u64 lapIn;

   u64stream lapOut;

  

   L1:for(int i=0; i<32; i++)

   {

       #pragma HLS PIPELINE

            lapIn.range(63,0) = *(aIn + i);

            lapOut.data = lapIn.range(63,0);

            aOut.write(lapOut);

   }

}


The module reads out words from DDR and sends them through the stream. Connecting to DDR through MIG. To start the IP module in vivado, I form the start pulses through the microblaze. In SDK I fill the DDR with a sequence of numbers. The input READY is connected with "1". ILA connect to interface lines m_axi and stream. The impulses start in the ILA are visible. The signals on the lines of the m_axi and the stream are equal to zero. What could be the problem?

 

 

 

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