ug871 design files error

[pkiang]

Problem with ug871-design-files

I am learning Vivado HLS following Vivado Design Suite Tutorial (ug871) with the downloaded ug871-design-files.

The problem happened on Chapter 8, Lab1.

The downloaded file ug871-design-files\RTL_Verification\lab1\run_hls.tcl doesn’t work.

Running the command vivado_hls -f run_hls.tcl failed.

[wenchen]

Hi @pkiang ，

      Could you provide some log when you run the .tcl file? Which version of HLS are you using?

Wen

[pkiang]

Please see attached 200317.docx

[jerhill]

I have the same result with this tutorial while running 2019.2:

@E Simulation failed: Function 'main' returns nonzero value '1'.
ERROR: [SIM 211-100] 'csim_design' failed: nonzero return value.
INFO: [SIM 211-3] *************** CSIM finish ***************
4
while executing
"source run_hls.tcl"
("uplevel" body line 1)
invoked from within
"uplevel \#0 [list source $arg] "

The only difference is that the original poster received "source [lindex $::argv 1] " in the fifth line. I have confirmed that I am using the most recent versions (as of May 2020) of ug871 and the accompanying zip file.

[jerhill]

Never mind, posted a little too quickly

The lab involves breaking the code so that it won't work. For whatever reason, the code that is included in the zip already has the break included.

duc_test.c lines 50 and 51 are

//return ((ret1 | ret2) ? 1 : 0);
return 1;

This should be simply

return ((ret1 | ret2) ? 1 : 0);

before the tutorial is performed.

This is an error in the distribution. Is there a mechanism for directly reporting issues like this, or do things just percolate up from the fora?

[aoifem]

Hi @jerhill 

Thanks for posting the workaround! 
This is a known issue and is due to be fixed in a future release. 

The best way to flag errors with us is to post on the forums and someone from Xilinx should be able to flag it internally. This way the community is aware of the issue and any potential workarounds. Thanks for your help! 

[jerhill]

Since you guys are paying attention, here are some other issues with UG871:

1. The issue addressed in https://forums.xilinx.com/t5/High-Level-Synthesis-HLS/UG871-example-fail-to-run-on-2018-2/td-p/877855 is still outstanding in 2019.2

2. Interface Synthesis Lab 1 file 'adders.c' includes line 49:

    #pragma HLS INTERFACE ap_ctrl_none port=return

      which is supposed to be added in the course of the lab but shouldn't be there at the start

3. UG871 p115 item 8 says 'click function dct_1d2' but based on image and following discussion, should probably be 'click function dct_2d'

4.Is the 'performance view' still present in 2019.2? UG902 p41 describes it, and UG871 refers to it in the description in page 115 item 9 and Figure 6-18 on p120. However, the analysis perspective opens to the Schedule/Resource viewer and there doesn't appear to be any way to access a 'performance' viewer.

5. UG871 pp. 168-169. The text says to set the trace to 'all' but Figure 8-11 show the setting as 'port'

Hope this helps!

-JMH