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Adventurer
Adventurer
578 Views
Registered: ‎12-19-2018

请问fpga的slice的构成都一样吗?实现时资源超了该如何优化?

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DSP48 SLICE和普通的slice是一样的嘛?fpga内部底层资源是怎样的?我布局布线的时候显示我用的资源超了该怎么改进呢?

[Place 30-640] Place Check : This design requires more Register as Flip Flop cells than are available in the target device. This design requires 1087729 of such cell types but only 866400 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.
[Place 30-640] Place Check : This design requires more Slice Registers cells than are available in the target device. This design requires 1087729 of such cell types but only 866400 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.
[Place 30-640] Place Check : This design requires more Slice LUTs cells than are available in the target device. This design requires 468216 of such cell types but only 433200 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. Please set tcl parameter "drc.disableLUTOverUtilError" to 1 to change this error to warning.
[Place 30-640] Place Check : This design requires more FDRE cells than are available in the target device. This design requires 1084500 of such cell types but only 868200 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.

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Moderator
Moderator
526 Views
Registered: ‎11-04-2010

Re: 请问fpga的slice的构成都一样吗?实现时资源超了该如何优化?

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SLICEM  可以配置成LUT,也可以配置成Distributed RAM(分布式RAM)和移位寄存器(SLR).

Block RAM 是专用的大块的RAM,和SLICE资源无关, DRAM转成BRAM可以一定程度下减小寄存器数目的压力. 实际的效果要看你设计中有多少逻辑适合类似的转换

你可以在IP catalog 中例化BRAM.

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Moderator
Moderator
570 Views
Registered: ‎11-04-2010

Re: 请问fpga的slice的构成都一样吗?实现时资源超了该如何优化?

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Hi, @chourching ,

你的设计中使用了过多的寄存器.

可以考虑是否有可能把一部分逻辑在DSP或者BRAM中实现. 如果寄存器还是太多,只能使用更大的器件或者减少你的逻辑.

DSP和普通逻辑的SLICE不是相同的结构.

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Adventurer
Adventurer
544 Views
Registered: ‎12-19-2018

Re: 请问fpga的slice的构成都一样吗?实现时资源超了该如何优化?

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请问怎么用BRAM代替寄存器呢,对verilog代码或综合实现过程如何处理?

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Adventurer
Adventurer
542 Views
Registered: ‎12-19-2018

Re: 请问fpga的slice的构成都一样吗?实现时资源超了该如何优化?

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distributed RAM是不是用的就是 普通SLICE 里的寄存器,而我所不够的资源正是普通slice的寄存器所以不能用distributed RAM?而BLOCK RAM并不用普通slice寄存器而是一个专门的存储区域,所以用BRAM可以解决我的问题?

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Moderator
Moderator
527 Views
Registered: ‎11-04-2010

Re: 请问fpga的slice的构成都一样吗?实现时资源超了该如何优化?

Jump to solution

SLICEM  可以配置成LUT,也可以配置成Distributed RAM(分布式RAM)和移位寄存器(SLR).

Block RAM 是专用的大块的RAM,和SLICE资源无关, DRAM转成BRAM可以一定程度下减小寄存器数目的压力. 实际的效果要看你设计中有多少逻辑适合类似的转换

你可以在IP catalog 中例化BRAM.

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-------------------------------------------------------------------------

View solution in original post

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