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Voyager
Voyager
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Registered: ‎05-14-2017

[2019.2] [DRC RTSTAT-1] Unrouted nets: 1 net(s) are unrouted. The problem bus(es) and/or net(s) are design_1_i/oddr_0/inst/clk_out.

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Hi,

I am trying to drive a differential clock signal out from the FPGA. Following this post I decided to put an ODDR before the OBUF_DS as shown below:

Screenshot_2020-06-03_13-30-31.png

But this kind of design implementation ends up with the following errors:

[DRC RTSTAT-1] Unrouted nets: 1 net(s) are unrouted. The problem bus(es) and/or net(s) are design_1_i/oddr_0/inst/clk_out.
[DRC RTSTAT-2] Partially routed nets: 1 net(s) are partially routed. The problem bus(es) and/or net(s) are design_1_i/oddr_0/inst/clk_out_BUFGCE.
[DRC RTSTAT-1] Unrouted nets: 1 net(s) are unrouted. The problem bus(es) and/or net(s) are design_1_i/oddr_0/inst/clk_out.
[DRC RTSTAT-2] Partially routed nets: 1 net(s) are partially routed. The problem bus(es) and/or net(s) are design_1_i/oddr_0/inst/clk_out_BUFGCE.

What could be the reason that  makes Vivado to do not route the net oddr_0/inst/clk_out ?

Thanks.

s.

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1 Solution

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Highlighted
213 Views
Registered: ‎06-21-2017

Re: [2019.2] [DRC RTSTAT-1] Unrouted nets: 1 net(s) are unrouted. The problem bus(es) and/or net(s) are design_1_i/oddr_0/inst/clk_out.

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There is another line from the oddr clk_out port.  Where does it go?  The oddr output should only go to an I/O buffer.

View solution in original post

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Highlighted
214 Views
Registered: ‎06-21-2017

Re: [2019.2] [DRC RTSTAT-1] Unrouted nets: 1 net(s) are unrouted. The problem bus(es) and/or net(s) are design_1_i/oddr_0/inst/clk_out.

Jump to solution

There is another line from the oddr clk_out port.  Where does it go?  The oddr output should only go to an I/O buffer.

View solution in original post

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Voyager
Voyager
210 Views
Registered: ‎05-14-2017

Re: [2019.2] [DRC RTSTAT-1] Unrouted nets: 1 net(s) are unrouted. The problem bus(es) and/or net(s) are design_1_i/oddr_0/inst/clk_out.

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@bruce_karaffayou are right.

I was feeding also other IPs clock input with ODDR output, and this was generating troubles.

Thanks for ensuring.

s.

 

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