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Observer davidhuo
Observer
5,545 Views
Registered: ‎11-02-2012

A Erorr when use fpga_edline to change iodelay_value

device: v6x760

ise: 14.5

 

rtl:

 

IODELAYE1 #(

  .CINVCTRL_SEL ("FALSE"),

 .DELAY_SRC        ("I"),

 .IDELAY_TYPE      ("FIXED"),

.IDELAY_VALUE   (31),

.ODELAY_TPYE   (FIXED"),

.ODELAY_VALUE   (0),

.REFCLK_PREQUENCY(208.0),

.SIGNAL_PATTERN ("CLOCK")

)

IODELAY_DQS(

  .C (1'b0),

 .CINVCTRL (1'b0),

 .CLKIN (1'b0),

 .ODATAIN(1'b0),

 .DATAIN (1'b0),

 .IDATAIN(emdqs[0]),

 .DATAOUT(pad_in_dmc_dqs[0]),

 .CNTVALUEIN(5'h0),

 .CNTVALUEOUT(),

 .CE(1'b0),

 .INC(1'b0),

 .RST(1'b1),

 .T(1'b1)

);

 

Now I want to use fpga_edline to edit *.ncd file to change the IDELAY_VALUE

 

setattr comp dqs_iodelay[0].IODELAY_DQS config "......IDELAY_VALUE:2....."  # other paramters not change

 

I got several  drc errors, the pins of  the IODELAY are not connectivity(CNTVALUEOUT[4:0], T,ODATAIN,etc)

 

1. why this happen ?

2. How to do next ?

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1 Reply
Xilinx Employee
Xilinx Employee
5,523 Views
Registered: ‎07-01-2008

Re: A Erorr when use fpga_edline to change iodelay_value

Try running the "trim" command on the component you edited as documented in this AR:

http://www.xilinx.com/support/answers/21667.htm

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