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Observer
Observer
6,260 Views
Registered: ‎12-25-2007

A PAR challenge for tri-states

Hi,

 

I am trying to produce a hardware which needs speed and accuracy in timing. I will sum up the problem with a code.

 

if rising_edge(clk) then

   if wea = '1' then

      douta <= some_signal(15 downto 8);

   else

      douta <= (others => 'Z');

   end if;

 

   if web = '1' then

      doutb <= some_signal(7 downto 0);

   else

      doutb <= (others => 'Z');

   end if;

end if;

 

Here "wea" and "web" are generated from the same signal and they are at the same level but for speed purpose I am using "equiavlent_register_removal = NO" attribute for these signals. Also again for speed douta, doutb signals have the "IOB = TRUE" attribute.

 

Problem is when I use FPGA editor the tri-state enable bits for "douta" port are directly in the IOB cell, which is the thing I want

but when I observe the tri-state enable bit for the "doutb" port it is not in the IOB cell, besides it is far away from the IOB so there is a 2 ns delay between douta and doutb ports.

 

Although I am using the same kind of signals why this happens? Any ideas?

 

By the way I use ISE 9.2.04 and a virtex4 LX100.

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4 Replies
Highlighted
Historian
Historian
6,243 Views
Registered: ‎02-25-2008

Re: A PAR challenge for tri-states


eneserdin wrote:

Hi,

 

I am trying to produce a hardware which needs speed and accuracy in timing. I will sum up the problem with a code.

 

if rising_edge(clk) then

   if wea = '1' then

      douta <= some_signal(15 downto 8);

   else

      douta <= (others => 'Z');

   end if;

 

   if web = '1' then

      doutb <= some_signal(7 downto 0);

   else

      doutb <= (others => 'Z');

   end if;

end if;

 

Here "wea" and "web" are generated from the same signal and they are at the same level but for speed purpose I am using "equiavlent_register_removal = NO" attribute for these signals. Also again for speed douta, doutb signals have the "IOB = TRUE" attribute.

 

Problem is when I use FPGA editor the tri-state enable bits for "douta" port are directly in the IOB cell, which is the thing I want

but when I observe the tri-state enable bit for the "doutb" port it is not in the IOB cell, besides it is far away from the IOB so there is a 2 ns delay between douta and doutb ports.

 

Although I am using the same kind of signals why this happens? Any ideas?

 

By the way I use ISE 9.2.04 and a virtex4 LX100.


The tristate assignment should NOT be part of a synchronous process.

 

-a

----------------------------Yes, I do this for a living.
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Highlighted
Observer
Observer
6,233 Views
Registered: ‎12-25-2007

Re: A PAR challenge for tri-states

I only wonder. Why tristate assignment should NOT be a part of synchronous process? Is this a design rule or a drawback in terms of resource usage or something else?

 

Thanks in advance.

 

Regards,

 

Enes.

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Highlighted
Historian
Historian
6,223 Views
Registered: ‎02-25-2008

Re: A PAR challenge for tri-states


eneserdin wrote:

I only wonder. Why tristate assignment should NOT be a part of synchronous process? Is this a design rule or a drawback in terms of resource usage or something else?

 

Thanks in advance.

 

Regards,

 

Enes.


 

THINK HARDWARE. What output would you expect to see if the input to a real flip-flop was tristated?

 

-a

----------------------------Yes, I do this for a living.
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Highlighted
Observer
Observer
6,209 Views
Registered: ‎12-25-2007

Re: A PAR challenge for tri-states

Yes you are right doing it combinatorial is the best. But XST is handling this kind of operation, I think, such that it is creating tristate enables for the output buffer. Since I use IOB property it puts the enable flip-flop just next to the IOB cell.

 

By the way for the problem I wrote I found a solution such that I am creating an enable signal bus as the same width as the output port and using it bit by bit.

 

Thank you for the valuable information.

 

Regards,

 

Enes

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