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susantha
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Registered: ‎01-31-2016

A Vivado project - unable to find the problem

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I have implemented an algorithm to find the mod value of two inputs. It has a datapath and an FSM Controller. I did the post-synthesis functional simulation and post-synthesis timing simulation. Functional simulation gives the right outputs while the timing simulation did not give any output. I could not see all my signals in vivado simulator, may be due to optimizatin the signals are changed or renamed. Therefore, I couldn't follow signals according to the algorithm to find the reason why timing simulation doesn't work.

 

Then I forced not to optimize the FSM Controler module and synthesized the system. After that I could run the timing simulation to get the right outputs. When I implemented on the FPGA hardware, I get right outputs for some input values while few outputs are wrong. I simulated those input combinations which resulted in wrong outputs, and found that the simulation gives correct outputs. Therefore I think the algorithm is correct. Vivado gives few warnings but they aren't critical. According to the Timing report there are not timing voilations too.

 

Now I am thinking how to fix the problem in this system. When implemented in hardware it gives right output most of the time with few wrong outputs; but when simulated it gives the correct answers. Any suggestion to fix the issue in the system?

 

Vivado version: 2015.4

Target board : Digilent Zybo board.

 

Thanks

-Susantha

 

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susantha
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I solved the problem. :)

I noticed that for the same input it gives right answer and wrong answer time to time. Then I did functional simulation to trace why that happens. Any input combination given first time, it works. When I give a series of input combination one after another, it gives wrong answers sometimes. The problem was that, I had an Incrementer which is not cleared when a new set of input is given. I changed the code to set the Incrementer to zero every time a new set of inputs are given. After that, the system simulate works and hardware implementation works as expected.

-Susantha

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muzaffer
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how are you supplying the input to the simulation and hardware? Are they properly synchronized?
In terms of the failing cases, is there any correlation between them? Are they large numbers, small numbers, randomly distributed ?
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susantha
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Inputs are two 32-bt numbers. I randomly input the test vector for both simulation and hardware test. Some input numbers were large and some were small. 

 

For hardware testing, I created a custom IP and connected it to zynq PS. Inputs and outputs are tied to memory locations in PS, and through a c-program different inputs are fed and  outputs are read from the memory.

 

I think the system is well synchronized. The controll signal outputs of the FSM Controller are also synchronized. 

 

I have not observed any correlations of the inputs and failing cases. I will distribute the inputs from small to large numbers and observe any correlation when they fail.

 

Thank you for your response.

-Susantha

 

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susantha
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Registered: ‎01-31-2016

I solved the problem. :)

I noticed that for the same input it gives right answer and wrong answer time to time. Then I did functional simulation to trace why that happens. Any input combination given first time, it works. When I give a series of input combination one after another, it gives wrong answers sometimes. The problem was that, I had an Incrementer which is not cleared when a new set of input is given. I changed the code to set the Incrementer to zero every time a new set of inputs are given. After that, the system simulate works and hardware implementation works as expected.

-Susantha

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