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314 Views
Registered: ‎10-07-2016

A fixed 600ps delay IDELAY ?

I use IDELAYE2 and IDELAYCTRL to add delay time for a signal.

I found that the delay time = fixed delay + tap* IDELAY_VALUE.

Where can I find the introduction about this fixed delay.

The result I got is fixed delay =600ps. (Kintex 7)

I cannt find any introduction in DS182 and UG471.

I need help, THX.

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6 Replies
Scholar drjohnsmith
Scholar
294 Views
Registered: ‎07-09-2009

Re: A fixed 600ps delay IDELAY ?

The fixed delay is dependent upoon routing / layout , and is determined at implimentation time,

 

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271 Views
Registered: ‎10-07-2016

Re: A fixed 600ps delay IDELAY ?

Hi Thanks for your answer.
Can I use IDELAY for a internal signal ,not for a physical PIN?
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Scholar drjohnsmith
Scholar
262 Views
Registered: ‎07-09-2009

Re: A fixed 600ps delay IDELAY ?

Nope. The Idelay block connects to IO pins at one end.

time to ask , what you trying to do ?
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227 Views
Registered: ‎10-07-2016

Re: A fixed 600ps delay IDELAY ?

I want to implement a Delay Unit which could be adjusted dynamic. Up to 1 ms range , 0.1 ns step resolution.
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Scholar drjohnsmith
Scholar
214 Views
Registered: ‎07-09-2009

Re: A fixed 600ps delay IDELAY ?

there are a few others on the forums doing the same,
basicaly you need a counter,
but as it can't run at 10 Ghz, you interpolate
A few ways to do this, a quick sugestion to get you thinking,
If you had two counters running at say 500 MHz,
but one on the rising edge , one on the falling edge,
then if you grab both counters at once, you can work out to 1000 MHz resolution where you are.

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Xilinx Employee
Xilinx Employee
194 Views
Registered: ‎07-16-2008

回复: A fixed 600ps delay IDELAY ?

With regards to the delay when tap=0, please have a look at this answer.

https://www.xilinx.com/support/answers/42133.html

 

You can drive IDELAY with either IOB or FPGA logic. For internal signal, connect it to DATAIN input rather than IDATAIN, and set DELAY_SRC to DATAIN.

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