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314 Views
Registered: ‎07-23-2019

ARM IP design empty

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I gave the ARM M-1 core a go and vivado failed to implement ("the design is empty") a basic BD with it and a clock generator, processor reset and AXI FIFO... why?

Note: yes, I created the wrapper and connected some pins as ports. I checked the BD.

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250 Views
Registered: ‎01-16-2013

Re: ARM IP design empty

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@archangel-lightworks 

 

If you see the ports declaration there are only input ports and no output ports. With no output ports, the tool optimizes all the logic giving you empty design. This is expected.

Looks like you are new to HDL language. I would suggest you refer few books/material on learning synthesizable HDL coding.

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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313 Views
Registered: ‎01-16-2013

Re: ARM IP design empty

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@archangel-lightworks 

 

Check if the block design validation was successful. On your error, "the design is empty" there must be no outputs or loadless signals. Check the runme.log file present in .runs/impl_1 folder to know about the logic getting optimized.

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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283 Views
Registered: ‎07-23-2019

Re: ARM IP design empty

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Yes, the block diagram is validated. It's like this:

err1.png

And the message is:

err2.png

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Registered: ‎01-16-2013

Re: ARM IP design empty

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@archangel-lightworks 

 

When you created the RTL wrapper around this block design, Do you seen any output ports in RTL?  I believe the design is completely getting optimized as there are no output ports. 

 

--Syed

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Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
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273 Views
Registered: ‎07-23-2019

Re: ARM IP design empty

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There are, all the ports you see in the BD.

I just run the wrapper as a top file, this is not anything serious, I just wanted to get a quick comparison with microblaze in terms of resource usage but I was surprised it didn't do it

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271 Views
Registered: ‎01-16-2013

Re: ARM IP design empty

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@archangel-lightworks 


Can you share your top module RTL file which the tool has created for BD?

 

--Syed

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262 Views
Registered: ‎07-23-2019

Re: ARM IP design empty

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Sure,

`timescale 1 ps / 1 ps

module bd_1_wrapper
   (CFGITCMEN,
    DBGRESETn,
    SWCLKTCK,
    clk_25MHz,
    nTRST,
    reset_rtl_0,
    reset_rtl_0_0);
  input [1:0]CFGITCMEN;
  input DBGRESETn;
  input SWCLKTCK;
  input clk_25MHz;
  input nTRST;
  input reset_rtl_0;
  input reset_rtl_0_0;

  wire [1:0]CFGITCMEN;
  wire DBGRESETn;
  wire SWCLKTCK;
  wire clk_25MHz;
  wire nTRST;
  wire reset_rtl_0;
  wire reset_rtl_0_0;

  bd_1 bd_1_i
       (.CFGITCMEN(CFGITCMEN),
        .DBGRESETn(DBGRESETn),
        .SWCLKTCK(SWCLKTCK),
        .clk_25MHz(clk_25MHz),
        .nTRST(nTRST),
        .reset_rtl_0(reset_rtl_0),
        .reset_rtl_0_0(reset_rtl_0_0));
endmodule

I wonder if it's so smart it ignores everything because there is no output (?)

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Moderator
Moderator
251 Views
Registered: ‎01-16-2013

Re: ARM IP design empty

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@archangel-lightworks 

 

If you see the ports declaration there are only input ports and no output ports. With no output ports, the tool optimizes all the logic giving you empty design. This is expected.

Looks like you are new to HDL language. I would suggest you refer few books/material on learning synthesizable HDL coding.

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------

View solution in original post

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242 Views
Registered: ‎07-23-2019

Re: ARM IP design empty

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HDL textbooks are useful and it's always good to go back to them as my first FPGA project was with some Lattice chip in the 90s.

But they won't tell about how Vivado optimizes HDL. That's not in the VHDL or Verilog standards.