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Observer deepwavebill
Observer
553 Views
Registered: ‎08-09-2018

AXI4-lite register implementation problems

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I have created an array of 16 AXI4-lite registers using the Vivado Tools-> Create and Package New IP-> Create AXI Peripheral. I was able to generate the Verilog module and edit it to add my outputs from the registers. I have attached the code: axi4_lit_reg_intrfc_M05.v. In my design it is connected in the top level to one master port of the AXI4 Cross-connect IP which has a single slave port and 6 master ports. 

I get through synthesis fine, but when I run implementation I get the following errors:

  • [DRC MDRV-1] Multiple Driver Nets: Net jesd204b_top_inst/jesd204_dwd_inst/jesd204_dwd_4ch_rx_tx_wrapper_inst/ has multiple drivers: jesd204b_top_inst/jesd204_dwd_inst/jesd204_dwd_4ch_rx_tx_wrapper_inst/GND/G, jesd204b_top_inst/jesd204_dwd_inst/jesd204_dwd_4ch_rx_tx_wrapper_inst/jesd204_dwd_4ch_rx_tx_i/axi_interconnect_0/xbar/inst/gen_sasd.crossbar_sasd_0/s_axi_bresp[1]_INST_0/O, and jesd204b_top_inst/jesd204_dwd_inst/jesd204_dwd_4ch_rx_tx_wrapper_inst/jesd204_dwd_4ch_rx_tx_i/axi_interconnect_0/xbar/inst/gen_sasd.crossbar_sasd_0/s_axi_bresp[0]_INST_0/O.

This signal is just set to 2'b0 by the code so it is hard to understand what else is driving this signal. I have also included my code for reference. I was setting the signal the same way and my code gets through Implementation, however my code hangs the PCIe bus when a register is accessed via the AXI4-Lite Master in the PCIe DMA core.

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Explorer
Explorer
505 Views
Registered: ‎05-21-2015

Re: AXI4-lite register implementation problems

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@deepwavebill,

Looking over the code you shared above, I could not find any issues with multiple drivers.  That said, since you only shared a portion of your project, I could not run the tools I usually use for finding multiple driver issues.  These tools include Verilator and Yosys.  Both run faster than Vivado, both can find all kinds of bugs, Yosys will find multiple driver bugs.  Feel free to run these programs on your source code to see if the error message is any better.

Basically, a "multiple driver" error is caused by more than one piece of logic  trying to determine the value of any given wire or register.  I would recommend that you examine all of the locations where you find the identified wires set.  Pay extra attention to any sub-module references, to make certain that you aren't also setting the output to a module as well.

For my own purposes, however, I am in the process of testing a set of formal AXI-lite properties.  These properties are written to be compatible with the open source formal solver SymbiYosys, and they are published on github.  Using these properties, I found multiple critical bugs within your dwd_car_bd_axi4_lite_regs.v file.  You can find my comments attached.  I did not find any bugs in your axi4_lite_reg_intrfc_M05 file.

While Verilator gave me many warnings for the two jesd*.v files, I did not find any actual errors within them--mostly because I had no access to the rest of your design, and so was unable to examine the submodules beneath these two.


Hope this helps,

Dan

3 Replies
Explorer
Explorer
506 Views
Registered: ‎05-21-2015

Re: AXI4-lite register implementation problems

Jump to solution

@deepwavebill,

Looking over the code you shared above, I could not find any issues with multiple drivers.  That said, since you only shared a portion of your project, I could not run the tools I usually use for finding multiple driver issues.  These tools include Verilator and Yosys.  Both run faster than Vivado, both can find all kinds of bugs, Yosys will find multiple driver bugs.  Feel free to run these programs on your source code to see if the error message is any better.

Basically, a "multiple driver" error is caused by more than one piece of logic  trying to determine the value of any given wire or register.  I would recommend that you examine all of the locations where you find the identified wires set.  Pay extra attention to any sub-module references, to make certain that you aren't also setting the output to a module as well.

For my own purposes, however, I am in the process of testing a set of formal AXI-lite properties.  These properties are written to be compatible with the open source formal solver SymbiYosys, and they are published on github.  Using these properties, I found multiple critical bugs within your dwd_car_bd_axi4_lite_regs.v file.  You can find my comments attached.  I did not find any bugs in your axi4_lite_reg_intrfc_M05 file.

While Verilator gave me many warnings for the two jesd*.v files, I did not find any actual errors within them--mostly because I had no access to the rest of your design, and so was unable to examine the submodules beneath these two.


Hope this helps,

Dan

Observer deepwavebill
Observer
264 Views
Registered: ‎08-09-2018

Re: AXI4-lite register implementation problems

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Thanks for the thorough analysis of my code. Based on your analysis I am going forward with axi4_lite_reg_intrfc_M05  code as my baseline.

I was able to trace through the layers of hierarchy and found that at one level the s_axil_bresp signal was designated an input instead of an output and this was causing the multiple driver error.

 

Thanks again for your help.

 

 

Bill

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Moderator
Moderator
125 Views
Registered: ‎01-16-2013

Re: AXI4-lite register implementation problems

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@deepwavebill

 

Any update on this thread? This forum post is open and waiting for your reply.

 

--Syed

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