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spagen
Newbie
Newbie
319 Views
Registered: ‎01-14-2021

Abnormal program termination (EXCEPTION_ACCESS_VIOLATION)

I am using the tcl interface to compile an Artix design. I started with the tcl of a fellow designer (whose design is very similar to mine), made a few edits to the files used in the design and reran, however while synthesis works I get this cryptic error during implementation with no other explanation. 

Here is a larger snippet of my compile transcription right around where it fails. 

Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1625.473 ; gain = 0.758
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
INFO: [Opt 31-1021] In phase Post Processing Netlist, 19 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 125 | 142 | 17 |
| Constant propagation | 57 | 499 | 18 |
| Sweep | 113 | 739 | 114 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 19 |
-------------------------------------------------------------------------------------------------------------------------

 

Starting Connectivity Check Task

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.046 . Memory (MB): peak = 1625.473 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 2566d9a48

Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1625.473 ; gain = 0.758

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Power 33-23] Power model is not available for a0/d0/dna0
Abnormal program termination (EXCEPTION_ACCESS_VIOLATION)
Please check 'C:/projects/wfirst_ps/trunk/assemblies/pmc/board/verification/functional/PmcTvs/par/xem7310/pmc_tvs_fpga/pmc_tvs_fpga.runs/impl_1/hs_err_pid19144.log' for details
[Thu Jan 14 19:28:24 2021] impl_1 finished
WARNING: [Vivado 12-8222] Failed run(s) : 'impl_1'

 

The log cited does not contain any detail. 

Stack:
no stack trace available, please use hs_err_<pid>.dmp instead.

 

The dmp is not readable. but attached. 

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drjohnsmith
Teacher
Teacher
312 Views
Registered: ‎07-09-2009

 run opt_design with -debug_log 

 

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