About Using SLR Crossing Registers

[enmingli]

I have the design requirement of placing more than 1000 groups of register pair between SLR1 and SLR2. In according to Page274&275 of ug949, a register-to-register connection should be manually placed onto a TX_REG to RX_REG connection. A reliable method of mapping registered crossings to Laguna is to apply both BEL and LOC constraints to the registers to lock them in place. 

Is there the constraint for a group of registers？ If not, do I have to write the constraint one by one?

[marcb]

Hi @enmingli 

If you have the ability to use Vivado 2018.3, there is a newly added property to constrain FFs to Laguna sites (crossing an SLR). This would be the USER_SLL_REG property. As long as the connectivity meets the requirements (listed in UG912), Vivado will attempt to place these FFs into Laguna sites.

set_property USER_SLL_REG TRUE [get_cells <cell_name>]

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug912-vivado-properties.pdf#page=367

Otherwise, a pblock can be used to group these FFs together and ranging the pblock to clock regions that include the Laguna registers you wish to use.

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[enmingli]

Currently, I only can use Vivado 2018.2. In my constraint file, there is the pblock region that includes the LAGUNA registers. But, when runing Vivado implementation, the errors are raised.

resize_pblock [get_pblocks {pblock_u0_nonce_ff}] -add {LAGUNA_X16Y480:LAGUNA_X23Y515}
resize_pblock [get_pblocks {pblock_u1_nonce_ff}] -add {LAGUNA_X16Y444:LAGUNA_X23Y479}

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ImplementationPlace Design[Place 30-786] Connectivity Legality - Laguna TX register [pcie_app_uscale_i/PIO_i/pio_ep/u_mining_sha3_256/u_mining_core_top_sha3/gen0.inst[0].u_search_nonce_sha3/u_keccak_2parts/ff2/state_out_reg[0][2][17]] needs to have at least one of its loads on a SLR across the inter-SLR channel connected to that BEL as well as none of its loads can reside on a Laguna RX register. If a register is constrained to a Laguna TX site, it is also necessary to constrain one of its loads to the adjacent SLR
[Place 30-99] Placer failed with error: 'Error in Laguna Register Connectivity Check'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
[Common 17-69] Command failed: Placer could not place all instances

[marcb]

Hi @enmingli

Is this an UltraScale or UltraScale Plus design? For UltraScale, you are limited to having the following connections:

TX Laguna -> SLICE FF (across SLR)

SLICE FF -> RX Laguna (across SLR)

Does the pblock allow for this? Do the constraints on the SLR crossing cells violate the restrictions indicated in the error?

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[enmingli]

The device is virtex ultrascale plus。Now，I have to write a tcl script file and use 'for loop' to set the constraint for more than 1000 pair of registers one by one.

[marcb]

Hi @enmingli 

If it helps, the constraint syntax could be accomplished with a few lines of Tcl. From an open netlist, the below example should print out the syntax for the constraint into the console based on the search criteria in the first line. This can be copied to an XDC file.

set laguna_cells [get_cells -hier -filter {NAME=~*string_to_match*}]

foreach i $laguna_cells  {puts "set_property USER_SLL_REG TRUE \[get_cells \{$i\}\]"}

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[marcb · Accepted solution]

Hi @enmingli 

If you found that a response answered the original question, I would make sure to mark this as an accepted solution. This way other users can see if the information helped.

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