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Visitor gccinac
Visitor
6,256 Views
Registered: ‎07-28-2013

Add hard macro external pin doubt

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Hi!

 

After following these steps [1] to instantiate a hard macro on my design I've some troubles "adding external macro pins" to my design.

 

Here a picture of FPGA Editor component's list:

component lists

 

I suppose that I should unplace ena_clk1_i and ena_clk0_i and S0_o as they are IBUF and IOB respectively and replace them with an external macro pin. Am I correct? If so... the IOB where S0_o is, is routed to two slices. Should I add a external macro pin to both? Should I use the same name or different name?

 

Thank you very much.

 

[1] http://www.xilinx.com/support/answers/10901.htm

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Xilinx Employee
Xilinx Employee
8,169 Views
Registered: ‎07-01-2008

Re: Add hard macro external pin doubt

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The slice components contain one or more instances from the logical design and the slice name is derived from an output net of the slice. To get the the correct instance names in FPGA Editor you should examine the BEL names. The slice attributes will list all BELs contained.

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Xilinx Employee
Xilinx Employee
6,246 Views
Registered: ‎07-01-2008

Re: Add hard macro external pin doubt

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Why are you creating a hard macro in the first place? There is very little that a hard macro can do that an RPM macro cannot and there are many pitfalls to their usage. I say this as perhaps the biggest advocate within Xilinx for maintaining hard macro support in ISE. It's good for creating configurations that Map cannot support but shoud otherwise be avoided. Please describe the problem you are trying to solve. There is likely a better way.

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Visitor gccinac
Visitor
6,236 Views
Registered: ‎07-28-2013

Re: Add hard macro external pin doubt

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I have two parts in my design: A critical part and a non critical part. The critical part is the one I'm trying to implement as a hard macro because I would like to test its behavior on different parts of the FPGA having always the same routing and relative placement between slices.

 

Is able a RPM to do that? If so,  I will replace the hard macro for an RPM.

 

The documentation I was able to find about this topic is this [1]. It says it is out of date. Is it still valid?

 

Thank you very much!

 

[1] http://www.xilinx.com/support/documentation/white_papers/wp329.pdf

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Community Manager
Community Manager
6,231 Views
Registered: ‎06-14-2012

Re: Add hard macro external pin doubt

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As suggested by Bret, RPM will be the way to go. Sometimes hard macros are diffcult to handle.

There is a good article on how to create RPMs.

 

http://www.xilinx.com/support/answers/51602.htm

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Visitor gccinac
Visitor
6,213 Views
Registered: ‎07-28-2013

Re: Add hard macro external pin doubt

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Thanks a lot for the answers

 

I tried to implement the RPM as both of you said. For than I'm writing on the .ucf file (as a starter):

 

INST "clk0/a_s" U_SET=myrpm;
INST "clk0/b_s" U_SET=myrpm;
INST "clk0/a_s" RLOC= X0Y0;
INST "clk0/b_s" RLOC= X9Y0;

And in the Translating step I get (4 times, one for each constraint):

 

ERROR:ConstraintSystem:59 - Constraint <INST "clk0/a_s" U_SET=myrpm;>
[source_e.ucf(1)]: INST "clk0/a_s" not found. Please verify that:

1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.

 

As my component exists (as you can see in the picture of the first post) and the spelling is correct, any ideas where the fail could be?

 

Thank you very much

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Xilinx Employee
Xilinx Employee
8,170 Views
Registered: ‎07-01-2008

Re: Add hard macro external pin doubt

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The slice components contain one or more instances from the logical design and the slice name is derived from an output net of the slice. To get the the correct instance names in FPGA Editor you should examine the BEL names. The slice attributes will list all BELs contained.

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Visitor gccinac
Visitor
6,202 Views
Registered: ‎07-28-2013

Re: Add hard macro external pin doubt

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Thank you!

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Xilinx Employee
Xilinx Employee
6,201 Views
Registered: ‎07-01-2008

Re: Add hard macro external pin doubt

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Another good source of RPM documentation is the RLOC section of the constraints guide.

 

This old app note I wrote covers some concepts that are still relevant:

http://www.xilinx.com/support/documentation/application_notes/xapp416.pdf

 

The slice structure for the newer architectures has changed (two slices per CLB vs. four) and so take that into account when reading the docs.

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Community Manager
Community Manager
6,197 Views
Registered: ‎06-14-2012

Re: Add hard macro external pin doubt

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The example in the AR was just about placing the two FFs. What does your Slice contain?

I am thinking that it might have more elements.

 

When applying an RLOC_RANGE, the individual elements of the RANGE (set) need to have their own RLOC. Essentially, you need to have an RPM and then create the RLOC_RANGE to specify the range to place the RLOC.

If you modify the above constraints as follows, then the RPM is created and placed within the range specified by the RLOC_RANGE constraint.

INST "LUT5_inst_0" U_SET=lut_set;
INST "LUT5_inst_1" U_SET=lut_set;
INST "LUT5_inst_2" U_SET=lut_set;
INST "LUT5_inst_3" U_SET=lut_set;
INST "LUT5_inst_4" U_SET=lut_set;
INST "LUT5_inst_5" U_SET=lut_set;
INST "LUT5_inst_6" U_SET=lut_set;
INST "LUT5_inst_7" U_SET=lut_set;
INST "LUT5_inst_0" RLOC=X0Y0;
INST "LUT5_inst_1" RLOC=X0Y1;
INST "LUT5_inst_2" RLOC=X0Y2;
INST "LUT5_inst_3" RLOC=X0Y3;
INST "LUT5_inst_4" RLOC=X1Y0;
INST "LUT5_inst_5" RLOC=X1Y1;
INST "LUT5_inst_6" RLOC=X1Y2;
INST "LUT5_inst_7" RLOC=X1Y3;
INST "LUT5_inst_0" RLOC_RANGE=X0Y2:X1Y7;

 

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Xilinx Employee
Xilinx Employee
6,189 Views
Registered: ‎07-01-2008

Re: Add hard macro external pin doubt

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I don't recommend using RLOC_RANGE. It's better to assign the macro to an area group (pblock) and then range constrain the area group. To lock the macro to a specific location, RLOC_ORIGIN is used.