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tabbalalex
Newbie
Newbie
10,175 Views
Registered: ‎06-10-2008

Automatic clock placement failed -- ISE 10.1.03 -- Virtex4 xc4vlx200 -- ERROR:Place:467

How to deal with this? (I'm aware of http://www.xilinx.com/support/answers/23480.htm it is not clear though!)

 

ERROR:Place:467 - Automatic clock placement failed. Please attempt to analyze the Global clocking required for this design and either lock the clock placement or area locate the logic driven by the clocks so that the clocks may be placed in such a way that all logic driven by them may be routed. The main restriction on clock placement is that only 8 of 32 clocks sourced by Global buffers may enter a region. For further information see the "Global clocks" section in the Virtex-4 Hand-Book

 

Any suggestions please? 

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8 Replies
Anonymous
Not applicable
10,167 Views

This can be very design specific you ned to LOC teh CLKs so that none of the restrictions of Regional and Gloabl routing are viloated. These are explained in the Virtex 4 user guide: http://www.xilinx.com/support/documentation/user_guides/ug070.pdf on page 25 lists the availible resources.
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bwade
Scholar
Scholar
10,130 Views
Registered: ‎07-01-2008

The clock placer exists because of the need to manage the routing restrictions of the global clocks. Each clock region has global routing resources for up to eight clock domains in a Virtex-4 device or up to ten in a Virtex-5 deice. The clock placer has to first choose locations for each clock component, and then automatically control clock region usage using area constraints.  The clock placer prints a rather verbose report containing a distribution of the clock domains by clock region and a list of the constraints that were used to achieve that distribution.

 

If the clock placer fails to find a solution, the distribution report will allow you to identify the clock regions that are over utilized. Once you have identified the problem clock region(s) it is possible to take the constraints  generated by the automatic placement attempt and tweak them to alleviate the congested clock regions. Check for the follwing issues:

 

- Are there a number of components with various clocks constrained to the problem clock region i.e IO clocks? Can they be moved elsewhere?

- Is there a clock domain in the clock region  that could easily be constrained elsewhere? Check for a slice-only clock domains with non-critical timing requirements.

- Are there large components (PPC, BRAM, DSP, etc.) with multiple clocks that could be constrained elsewhere? 

 

Once you have decided on the constraint changes needed to  resolve the clock region congestion, move the clock placement constraints found in the map log file (.map) to your user constraints file (.ucf) and edit them appropriately. For a complex clocking structure It may take a few iterations to find a solution.

 

Message Edited by bwade on 12-04-2008 01:23 PM
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berufspenner
Explorer
Explorer
8,003 Views
Registered: ‎03-04-2010

I have just the same problem but these answers didn't helped me. Is there anything more to do to solve this problem? Out of sheer desperation I'm trying out the "xplorer.pl" script (http://www.xilinx.com/support/answers/21133.htm) but I don't know if it would brings me further. Is there any other possible way?
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ywu
Xilinx Employee
Xilinx Employee
7,994 Views
Registered: ‎11-28-2007

Can you post the error message? It'd help if you can also attach the .map file.
Cheers,
Jim
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berufspenner
Explorer
Explorer
7,988 Views
Registered: ‎03-04-2010

Thanks for your reply. The error message is right the same as above:

 

 ERROR:Place:467 - Automatic clock placement failed.  Please attempt to analyze the global clocking required for this
   design and either lock the clock placement or area locate the logic driven by the clocks so that that the clocks may
   be placed in such a way that all logic driven by them may be routed.  The main restriction on clock placement is that
   only 8 of 32 clocks sourced byglobal buffers may enter a region. For further information see the "Clock Resources"
   section in the V-4 User Guide

 Below I attached my *.map file.

 

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bwade
Scholar
Scholar
7,976 Views
Registered: ‎07-01-2008

This map report is from a non-timing driven run where no placement was attempted. Your failed clock placement must have occured in the PAR placer. I suggest trying a timing driven run (-timing option) and then providing the .map file from that run if it also fails.

 

Bret

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berufspenner
Explorer
Explorer
7,968 Views
Registered: ‎03-04-2010


bwade wrote:

This map report is from a non-timing driven run where no placement was attempted. Your failed clock placement must have occured in the PAR placer. I suggest trying a timing driven run (-timing option) and then providing the .map file from that run if it also fails.

 

Bret


How can make a timing driven run? Should mark "timing" in the project options "simulation models" or where should I set it?

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bwade
Scholar
Scholar
7,944 Views
Registered: ‎07-01-2008

Timing driven  mapping is done on V4 devices when the -timing switch is used. In the GUI it's an advanced map property, "Perform Timing Driven Packing ..." The option is obsolete on newer architectures (V5, V6, S6) because the timing driven flow is on by default and is the only supported flow. 
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