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Explorer
Explorer
3,672 Views
Registered: ‎06-13-2013

Automatic clock placement failed

Hi I am having troubles implementing my design.

(Spartan 3a 400A)

I have 3 Clocks used in my FPGA:

1. 25 MHz clock input on GCLK10

2. 25 MHz clock input on LHCLK7  (X0Y9)

3. 125 MHz clkFX from the DCM using CLK 1.

 

It appears that the GCLK10 is being put into BUFGMUX H and that is competing with the X0Y9 Clock.  If you see the error below, how can I put GCLK10 into X1Y11?  Should I be not using the Clock that is inptu into the DCM and instead being using CLK0 of DCM as my CLK25? 

 

Place:1138 - Automatic clock placement failed. Please attempt to analyze the global clocking required for this
   design and either lock the clock placement or area locate the logic driven by the clocks so that the clocks may be
   placed in such a way that all logic driven by them may be routed. The main restriction on clock placement is that
   only one clock output signal for any competing Global / Side pair of clocks may enter any region. For further
   information see the "Quadrant Clock Routing" section in the Spartan3a Family Datasheet.

   The competing Global / Side clock buffers for this device are as follows:
   BUFGMUX_X2Y1 :    BUFGMUX_X0Y2
   BUFGMUX_X2Y0 :    BUFGMUX_X0Y3
   BUFGMUX_X1Y1 :    BUFGMUX_X0Y4
   BUFGMUX_X1Y0 :    BUFGMUX_X0Y5
  BUFGMUX_X2Y11 :    BUFGMUX_X0Y6
  BUFGMUX_X2Y10 :    BUFGMUX_X0Y7
  BUFGMUX_X1Y11 :    BUFGMUX_X0Y8
  BUFGMUX_X1Y10 :    BUFGMUX_X0Y9
   BUFGMUX_X2Y1 :    BUFGMUX_X3Y2
   BUFGMUX_X2Y0 :    BUFGMUX_X3Y3
   BUFGMUX_X1Y1 :    BUFGMUX_X3Y4
   BUFGMUX_X1Y0 :    BUFGMUX_X3Y5
  BUFGMUX_X2Y11 :    BUFGMUX_X3Y6
  BUFGMUX_X2Y10 :    BUFGMUX_X3Y7
  BUFGMUX_X1Y11 :    BUFGMUX_X3Y8
  BUFGMUX_X1Y10 :    BUFGMUX_X3Y9
Phase 5.30  Global Clock Region Assignment (Checksum:9d6ad587) REAL time: 28 secs

Total REAL time to Placer completion: 28 secs
Total CPU  time to Placer completion: 28 secs


Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|       sck_adc_OBUF* | BUFGMUX_X1Y10| No   |  728 |  0.000     |             |
+---------------------+--------------+------+------+------------+-------------+
|          clk125MHz* | BUFGMUX_X2Y11| No   |  133 |  0.000     |             |
+---------------------+--------------+------+------+------------+-------------+
|   fpga_bus_4_BUFGP* |  BUFGMUX_X0Y9| No   |   22 |  0.000     |             |
+---------------------+--------------+------+------+------------+-------------+
* Some of the Clock networks are NOT completely routed

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2 Replies
Xilinx Employee
Xilinx Employee
3,638 Views
Registered: ‎09-20-2012

Re: Automatic clock placement failed

Hi,

 

If you want to lock the conflicting BUFG instance in the design, you can use the below constraint in the UCF.

 

INST "bufg_instance_name" LOC = BUFGMUX_XxYy;

 

Thanks,

Deepika.

Thanks,
Deepika.
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Community Manager
Community Manager
3,612 Views
Registered: ‎06-14-2012

Re: Automatic clock placement failed

In general, when automatic clock placement fails, the reason can be one of several things: 
- a poor selection was made for the clock component placement 
- a poor clock region allocation was made for one or more clock domains 
- the clock structure is very complex and a placement solution is difficult or impossible to find 

 

What are your map options? If you have -timing, try a run by disabling them?

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