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ldm_gk
Participant
Participant
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Registered: ‎09-10-2020

BRAM Tile - what does it mean?

Hi All,

In the Utilization Report, Vivado reports the BRAM in Tiles.

What does it mean "BRAM Tile"? Where does its definition/structure appear in the documentation?   

Thank you!

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hongh
Moderator
Moderator
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Registered: ‎11-04-2010

The BlockRAM in UltraScale(Plus) architecture-based devices stores up to 36 Kbits of data and can be configured as either two independent 18 Kb RAMs, or one 36 Kb RAM.

That means one BRAM Tile can be configured as one RAMB36K or 2 RAMB18K.

 

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ldm_gk
Participant
Participant
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Registered: ‎09-10-2020

Thanks, but I also have another question ...

As for the Utilization report, there are Slices, Slice LUTs, Slice Regs, LUTs as Memory, and LUTs as Logic columns.

According to the numbers, LUTs as Logic + LUTs as Memory = Slice LUTs. But what's a number of Slices? What should represent this number? What is Slice of Registers?

Anyway, the SliceLUTs+Slice Regs are not equal to number of Slices in the report.

Should the LUTs-as-Memory + LUTs-as-Logic be equal to Slice LUTs? What's about the Slice Registers number? Is this number the same as a number of FFs in the Product Selection Guide?

Thank you!

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hongh
Moderator
Moderator
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Registered: ‎11-04-2010

Please refer to the below discussion and Doc UG574 for better understanding:

https://forums.xilinx.com/t5/Implementation/Vivado-utilization-report/td-p/317517

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