I reimplemented an "old" design from Planahead 14.2 to Vivado 2014.2 (versions are confusing but I double checked).
The design contains some FIFOs. In Planahead I noted that after using Coregen correctly the design used about 50% of the nativ FIFOs and 0% BRAM. If done incorrectly almost all BRAM were used and no nativ FIFOs.
In Vivado I created a custom IP Block. This block then contains a generated IP Core configuring a nativ FIFO. After packing my custom block it is used in a over all system design. Implementeation (and even bitfile creation) works. BUT it seems to use all my BRAM and no nativ FIFOs. I am completely stuck. I can not "add" the FIFO IP to the final project since it complains that its already there (even tough I cant see it under IP).
One thing worth mentioning. While packing my custom IP Block I chose "include .XCI file". But the there was a warning about the source beeing outside my design. Since beeing outsinde my design is kind of the definition for an IP Block I did not bother.
What is the diffrence of "include .XCI" and "include generated files" when packing an IP into an IP?
How can I enforce the implementation to use nativ FIFOs if defining it in the generated IPCore is not enough?
Can I enforce Vivado to show me resources that are not used? So I could see in the implementation not only the green bar on BRAM but also FIFO and then kind of no bar so I know it does not confuse those memory resources?
Its a zynq design so I am pretty sure that there are FIFOs...