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Visitor nilnullzip
Visitor
210 Views
Registered: ‎09-19-2018

BUFG not inserted for high fanout net

I found this long path not addressed by BUFG insertion. It's a global signal that goes throughout the FPGA. Seems counter intuitive because BUFG was inserted post placement in other signals with lesser fanout. See transcript. And I think there are enough BUFGs to allow this one to be buffered too. See clock utilization report.

I'm curious if perhaps BUFG insertion does not occur for SLR crossings? Or are there other explanations for why this one would not be buffered while the others were?

-Juan

 

Screen Shot 2019-01-02 at 5.27.52 PM.png

 

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 1a983338c

Phase 4.1.1.1 BUFG Insertion
INFO: [Place 46-35] Processed net WRAPPER_INST/CL/ms_periph_inst/c/p[2080]_i_1_n_0, inserted BUFG to drive 4160 loads.
INFO: [Place 46-35] Processed net WRAPPER_INST/CL/ms_periph_inst/c/square_lsb[2077]_i_1_n_0, inserted BUFG to drive 2078 loads.
INFO: [Place 46-31] BUFG insertion identified 2 candidate nets, 2 success, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason.
Phase 4.1.1.1 BUFG Insertion | Checksum: 14525a5c6

 

+------------+------+-----------+-----+--------------+--------+
| Type | Used | Available | LOC | Clock Region | Pblock |
+------------+------+-----------+-----+--------------+--------+
| BUFGCE | 18 | 720 | 12 | 0 | 18 |
| BUFGCE_DIV | 1 | 120 | 1 | 0 | 1 |
| BUFGCTRL | 0 | 240 | 0 | 0 | 0 |
| BUFG_GT | 23 | 720 | 23 | 0 | 23 |
| MMCM | 4 | 30 | 4 | 0 | 4 |
| PLL | 4 | 60 | 0 | 0 | 0 |
+------------+------+-----------+-----+--------------+--------+

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4 Replies
Xilinx Employee
Xilinx Employee
172 Views
Registered: ‎05-08-2012

Re: BUFG not inserted for high fanout net

Hi @nilnullzip.

Is a reproducible post-synthesis DCP available? If the fanout is over 25K and if there are less than 24 BUFGs, then I would expect the BUFG insertion.


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Visitor nilnullzip
Visitor
168 Views
Registered: ‎09-19-2018

Re: BUFG not inserted for high fanout net

Thanks for the reply! I don't know that I can reproduce it at this point. My design takes 24hrs to build and I'm right now just trying to get something to work. So I eliminated that net rather than try to isolate the reason. I thought it an interesting observation and tried to capture all of the relevant info to report.

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Moderator
Moderator
119 Views
Registered: ‎01-16-2013

Re: BUFG not inserted for high fanout net

@nilnullzip

 

Was there any DONT_TOUCH attribute on the cell or net which was not allowing the BUFG insertion. If you encounter the issue again then please share the post synth dcp to debug the issue. 

 

--Syed

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Visitor nilnullzip
Visitor
112 Views
Registered: ‎09-19-2018

Re: BUFG not inserted for high fanout net

No dont_touch. However there was a keep_hierarchy=yes on the enclosing module. Would that have the same effect?

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