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sureshraj
Observer
Observer
388 Views
Registered: ‎09-11-2014

BUFG on high fan out net driven by general purpose I/O

Hi,

In opt_design , vivado inserted a BUFG on high fanout nets but the net is being driven from Normal I/O.

But eventually , place_design failed with Sub-optimal placement.

Below is the messages from opt_design and place_design.

Is there a way to globally convert the ERROR to warning? Or to disable the BUFG insertion completely?

Vivado should be able to identify that high fanout net was driven by I/O and automatically add CLOCK_DEDICATED_ROUTE constraint.

Opt_design:

Phase 4 BUFG optimization
INFO: [Opt 31-194] Inserted BUFG uIBUFDS_GCLK1_BUFG_inst to drive 673029 load(s) on clock net uIBUFDS_GCLK1_BUFGCE
INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets
INFO: [Opt 31-129] Inserted BUFG to drive high-fanout reset|set|enable net. BUFG cell: uboston_logic/uhubble_ss_top/uhubble_pd2_top/uvc8000e_top/u_part0/u_clock_and_reset/u_std_cell_dff_reset_module_nn/reset_module_n_BUFG_inst, Net: uboston_logic/uhubble_ss_top/uhubble_pd2_top/uvc8000e_top/u_part0/u_clock_and_reset/u_std_cell_dff_reset_module_nn/reset_module_n
INFO: [Opt 31-129] Inserted BUFG to drive high-fanout reset|set|enable net. BUFG cell: sig_uhubble_pdnpg_top_pdnpg_pd2_VC_core_rstn_c_BUFG_inst, Net: sig_uhubble_pdnpg_top_pdnpg_pd2_VC_core_rstn_c.

 

But in place design with the below error.

 

ERROR: [Place 30-675] Sub-optimal placement for a global clock-capable IO pin and BUFG pair.If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.ERROR: [Place 30-675] Sub-optimal placement for a global clock-capable IO pin and BUFG pair.If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule. < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sig_uhubble_pdnpg_top_pdnpg_pd2_VC_core_rstn_ibuf/O] >

-Suresh

 

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2 Replies
syedz
Moderator
Moderator
201 Views
Registered: ‎01-16-2013

@sureshraj 

 

Can you share the post opt dcp file with us which should be located at .runs/impl_1 folder? You can try applying "CLOCK_BUFFER_TYPE" attribute to "NONE" so that tool does not insert BUFG.  Check page 170 in UG912 user guide for syntax details: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug912-vivado-properties.pdf#page=170  

 

Or use the below command in XDC file:

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sig_uhubble_pdnpg_top_pdnpg_pd2_VC_core_rstn_ibuf/O]

 

--Syed

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surajc
Xilinx Employee
Xilinx Employee
131 Views
Registered: ‎01-30-2019

Hi @sureshraj 

In the error message, the tool is trying to say that the input to BUFG is coming from a GCCIO pin, but in your first line, you mentioned that it is a Normal IO.
Could you check this once and make sure that you are using normal IO? 
If that is confirmed then you need to follow Syed's CLOCK_DEDICATED_ROUTE constraint. 

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