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Visitor jczarn1
Visitor
4,483 Views
Registered: ‎08-28-2012

BUFG usage reporting

Hello,

 

I am trying to analyze BUFG usage on a Spartan6 project that I am working on.  We are using ISE/XST.  We are going to be adding some IP that requires a certain number of BUFGs, so I want to make sure there are enough available and locate and remove any BUFGs that are not truly necessary.

 

The .syr file tells me that I am using a total of 15 clock buffers, including 10 BUFG and 5 BUFGMUX.

It summarizes "number of BUFG/BUFGCTRLs: 15 out of 16  (93%)"

 

At the top of the .mrp file, under specific feature utilization, it lists:

"Number of BUFG/BUFGMUXs: 13 out of 16 (81%)", which it breaks down to 8 BUFG and 5 BUFGMUX

 

Yet, further down in the .mrp file, under "Utilization by Hierarchy", it lists BUFG usage as 8 in the total project.  There is no mention of BUFGMUX.  This appears to be the same as the data displayed by clicking "Module Level Utilization" in the ISE gui. 

 

Can anyone explain these discrepancies?  How many BUFGs/BUFGMUXs am I actually using?  And is there a way to figure out how many each module is using?  It appears that the module level utilization is not reporting BUFGMUX, even though I believe BUFG and BUFGMUX use the same physical device on silicon.

 

Thanks in advance!

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3 Replies
Professor
Professor
4,475 Views
Registered: ‎08-14-2007

Re: BUFG usage reporting

You can open the design in FPGA editor, and then look at all components.  Click on the title for

component type (This is from memory - it may be called something else, but it's the column where you

can see things like SLICE) to sort by type and then you can count the BUFG(MUX)es.

 

It sounds like XST created more clock buffers than necessary and then the Map process took

some out or perhaps merged clocks that were equivalent.

 

You could also make sure that Map is set to produce a detailed (or verbose - I forget) report and

then look at the "module level usage" from the Design Summary view.

 

-- Gabor

-- Gabor
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Xilinx Employee
Xilinx Employee
4,473 Views
Registered: ‎07-01-2008

Re: BUFG usage reporting

You can also get a lot of details on the global clock utilization this way:

reportgen -clock_regions xyz.ncd

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Xilinx Employee
Xilinx Employee
4,422 Views
Registered: ‎11-28-2007

Re: BUFG usage reporting

You may find the "Component View" in ADEPT helpful. See the post below for more details:

 

http://myadeptblog.blogspot.com/2009/12/virtex5-component-view.html

 


@jczarn1 wrote:

Hello,

 

I am trying to analyze BUFG usage on a Spartan6 project that I am working on.  We are using ISE/XST.  We are going to be adding some IP that requires a certain number of BUFGs, so I want to make sure there are enough available and locate and remove any BUFGs that are not truly necessary.

 

The .syr file tells me that I am using a total of 15 clock buffers, including 10 BUFG and 5 BUFGMUX.

It summarizes "number of BUFG/BUFGCTRLs: 15 out of 16  (93%)"

 

At the top of the .mrp file, under specific feature utilization, it lists:

"Number of BUFG/BUFGMUXs: 13 out of 16 (81%)", which it breaks down to 8 BUFG and 5 BUFGMUX

 

Yet, further down in the .mrp file, under "Utilization by Hierarchy", it lists BUFG usage as 8 in the total project.  There is no mention of BUFGMUX.  This appears to be the same as the data displayed by clicking "Module Level Utilization" in the ISE gui. 

 

Can anyone explain these discrepancies?  How many BUFGs/BUFGMUXs am I actually using?  And is there a way to figure out how many each module is using?  It appears that the module level utilization is not reporting BUFGMUX, even though I believe BUFG and BUFGMUX use the same physical device on silicon.

 

Thanks in advance!




Cheers,
Jim
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