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Visitor
Visitor
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Registered: ‎11-12-2020

Badly generated multiplier design through behavioural code

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Hello, 

I am trying to realize a 25 by 18 bit multiplier in Vivado using simple behavioural VHDL code

The synthesized design is generated using 2 DSP48E1 while in theory one DSP should suffice. It seems that Vivado routes the inputs so that the first DSP calculates part of the larger input multiplied by the full shorter input and the second DSP is used to yield the rest of the product. 

Even if I constrain the DSPs to be used to 1 in a custom strategy, Vivado implements the second DSP's function using LUTs.

I have managed to synthesize the a single DSP design using IP integrator to verify that a one DSP implementation is actually possible.

My guess is that DSPs are by default initialized to use 18 bit A and B inputs (as when initialized in IP integrator) that are not reconfigured to 25.

Is there a way to achieve a one DSP implementation of this multiplier without using the IP integrator?

I am new to Vivado so any additional advice for my approach is also welcome. 

Thanks in advance

- using xc7k70tfbv676-1

- vivado 2018

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Moderator
Moderator
416 Views
Registered: ‎11-09-2015

HI @DioSoto 

You can use a ADDMACC_MACRO (see UG953 page 185) or the DSP48E1 (see UG953 page 267). This is the best way to have the full control

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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Moderator
Moderator
417 Views
Registered: ‎11-09-2015

HI @DioSoto 

You can use a ADDMACC_MACRO (see UG953 page 185) or the DSP48E1 (see UG953 page 267). This is the best way to have the full control

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

400 Views
Registered: ‎01-22-2015

@DioSoto 

Using Vivado v2018.3 for Kintex-7, I find that the following VHDL code snippets result in use of one DSP48.

 

 

 

    signal V1 : signed(24 downto 0);
    signal V2 : signed(17 downto 0);
    signal R1 : signed(42 downto 0);

    attribute USE_DSP : string;
    attribute USE_DSP of R1 : signal is "YES";

    P1: process(CLK1)            
        begin    
            if rising_edge(CLK1) then   
                R1 <= V1 * V2;
            end if;           
    end process P1;  

 

 

 

However, if I change V1, V2, and R1 to be unsigned types then two DSP48 are used.

So, ensure you are using signed 25x18 multiply with DSP48 as recommended in document UG479.

Cheers,
Mark

 

Visitor
Visitor
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Registered: ‎11-12-2020

I have successfully sythesized, implemented and simulated a design with 1 DSP using the instantiation code on ug953 pg. 187. by replacing the default ADDMAC port assignments with the design's I/O and custom signals. 

Thank you @florentw  for pointing me in the right direction.

Note: in the Port Map of the ADDMACC_MACRO in the given code, PREADDER ports are actually declared as PREADD1 and PREADD2 for Vivado 2018.1

 

I have not tried out markg@prosensing.com 's solution, but it might be worth doing so in the future...

Thank you gentlemen,

Dio