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Adventurer
Adventurer
1,282 Views
Registered: ‎01-05-2017

Binary Counter IP

Hi, I' m trying to build a multichannel counter design using Binary Counter IP. However I didn't understand if it is possible to use it for pulse counting? 

There is a broder question. I' m trying to measure frequency of different signal inputs. When I apply a signal to one channel of a multi channel counter system, I observe counts on the empty channels. When I load all channels I observe a big shift and some oscillation on the counts. So I thought IP counter could be a solution for this. After reading the docs I ' m still not quiet sure if it counts pulses or not and how.

Thanks in advance. 

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22 Replies
1,252 Views
Registered: ‎01-22-2015

Re: Binary Counter IP

@macellan85 

I’m not familiar with the Binary Counter IP.  However, counting pulses is something you can easily code-up yourself.  Here’s the steps for doing this.

1) Use a Clock Management Tile (MMCM or PLL) to generate a timing/sampling clock, CLKS, whose period is less than 1/2 the narrowest-width of a pulse and less than 1/2 the narrowest-gap between pulses.

2) Bring your pulsed signal, PSIG, into the FPGA and route it through a single-bit synchronizer (eg. see XPM_CDC_SINGLE on page-26 of UG953(v2017.3)).   This synchronizer is necessary because edges of PSIG are asynchronous with CLKS.

3) Let PSIGS be the name of the output from the single-bit synchronizer. 

4) Use a process clocked by CLKS to register/sample PSIGS and to count rising-edges found in the samples of PSIGS.  -which is equivalent to counting rising-pulses on PSIG.

5) When you start/stop counting rising-edges found on PSIGS you can also start/stop a counter for elapsed cycles of CLKS.  In this way you will have a time associated with the pulse-count from PSIG.

Mark

Teacher drjohnsmith
Teacher
1,196 Views
Registered: ‎07-09-2009

Re: Binary Counter IP

How are you at RTL code ( VHDL or SystemVerilog )

In VHDL a counter is relatively simple, and more general than a IP block. count is an unsigned,


Process( clk )
begin
if rising_edge( clk ) then
count <= count + 1;
end if;
end process;

As such, I'd not want to use an IP.



How to use a counter to count pulses.

Well, it depends first on how wide the pulse is compared to the counters clock.

You need to first make the pulse one clock wide,
https://surf-vhdl.com/how-to-design-a-good-edge-detector/

Then , use that pulse to enable the counter

Process( clk )
begin
if rising_edge( clk ) then
if enable = '1' then
count <= count + 1;
end if;
end if;
end process;


Now you have counter that counts up once on each pulse,

now what you want to do with this , is the next question.
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Adventurer
Adventurer
1,164 Views
Registered: ‎01-05-2017

Re: Binary Counter IP

I know what is a binary counter and already designed a multi channel version which works very well for several kHz region. However, for MHZ region (say 10MHz) one channel still works well but when you connect 5 channels it is not possible to have a value around 10M.  So I think the problem is not building a binary counter only but also I GUESS AND SEARCHING FOR NOW a kind of constraint problem. I just thought IP counter could be better optimized to use the resources and show better performance. Thus I'm trying to figure it out. 

Maybe my board is not capable of doing this. It is a very basic version (Elbert v2 - Spartan 3AN) but which one is a good candidate then and why?

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Teacher drjohnsmith
Teacher
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Registered: ‎07-09-2009

Re: Binary Counter IP

can you show us your code please.

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1,137 Views
Registered: ‎01-22-2015

Re: Binary Counter IP

@macellan85 

Here's some VHDL that implements the 2-flip-flop synchronizer (S2FF) and the pulse-counter that I described.

    signal CLKS,RST,RUN,PSIG,PSIGS,PSIGS_P,META_2FF : std_logic;        
    signal PCNT,SCNT : integer range 0 to 65535;
attribute ASYNC_REG : string; attribute ASYNC_REG of META_2FF, PSIGS: signal is "TRUE"; --2-flip-flop synchronizer S2FF: process(CLKS) begin if rising_edge(CLKS) then META_2FF <= PSIG; PSIGS <= META_2FF; end if; end process S2FF; --pulse counter PCT: process(CLKS) begin if rising_edge(CLKS) then if(RST = '1') then PCNT <= 0; SCNT <= 0; elsif(RUN = '1') then if((PSIGS = '1') and (PSIGS_P = '0')) then PCNT <= PCNT + 1; end if; SCNT <= SCNT + 1; else --do nothing end if; PSIGS_P <= PSIGS; end if; end process PCT;


     ...but also I GUESS AND SEARCHING FOR NOW a kind of constraint problem. 
You might be searching for the ASYNC_REG constraint shown in my VHDL above.  This constraint and the 2-flip-flop synchronizer are important and necessary for proper operation of the pulse counter.  Without them, registers used in the pulse counter can become metastable, which can cause erroneous pulse counts. 

You will need to verify that the ASYNC_REG constraint is working for the Spartan-3AN.

     Maybe my board is not capable of doing this.
Your board is capable of doing this.

Mark

 

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Adventurer
Adventurer
1,095 Views
Registered: ‎01-05-2017

Re: Binary Counter IP

Dear markg@prosensing.com and @drjohnsmith  thank you for your interest. I modified the my counter design depending on your example. However, I didn' t get a difference.

Regarding to ASYNC_REG... I just tried it and didn' t get any error. So it looks there is no problem with Spartan3AN.

Here is the final version ...

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Pulse_Counter_4 is
	Port( 	clk, RUN, RST, Pulse: IN  STD_LOGIC ;  -- 100 MHz / 10 ns
		POF	: IN  STD_LOGIC ;	-- Measurement period indicator
		TotalCount: OUT STD_LOGIC_VECTOR (23 downto 0) );
end Pulse_Counter_4 ;
architecture Behavioral of Pulse_Counter_4 is
signal s_Pulse : std_logic; signal s_Pulse_P : std_logic; signal META_2FF : std_logic; attribute ASYNC_REG : string; attribute ASYNC_REG of META_2FF, s_Pulse: signal is "TRUE"; begin S2FF: process(clk) begin if rising_edge(clk) then META_2FF <= Pulse; s_Pulse <= META_2FF; end if; end process S2FF;
Pulse_counting : process(clk, s_Pulse, POF, RST, RUN) variable PCNT : integer range 0 to 16E+6 := 0; variable SCNT : integer range 0 to 16E+6 := 0; -- I DIDN' T GET THE REASON OF THIS SECOND COUNT ?? begin if ( rising_edge(clk) ) then if ( RUN = '1' ) AND ( RST = '0' ) then if ( POF = '0' ) then -- Measurement period control flag if ( s_Pulse = '1' ) AND ( s_Pulse_P = '0' ) then PCNT := PCNT + 1 ; end if; else TotalCount <= std_logic_vector(to_unsigned(PCNT, 24)); PCNT := 0; end if; else PCNT := 0; TotalCount <= X"000000"; end if ; s_Pulse_P <= s_Pulse; end if; end process ; end Behavioral;

 

 

 

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Teacher drjohnsmith
Teacher
1,090 Views
Registered: ‎07-09-2009

Re: Binary Counter IP

lets see your test bench and simulatoin output of the problem

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1,079 Views
Registered: ‎01-22-2015

Re: Binary Counter IP

@macellan85 

The ASYNC_REG=TRUE property on  META_2FF and s_Pulse tells the Xilinx tools (ISE) to place these two registers physically close together inside the FPGA (in the same slice).  Then, the two registers and the synchronizer will properly fight metastability.

Using ISE, you should open your implemented design and verify that META_2FF and s_Pulse are in the same slice of the FPGA.

As drjohnsmith says, simulation is very important, but simulation will not show you pulse counter problems caused by metastability.

Adventurer
Adventurer
1,051 Views
Registered: ‎01-05-2017

Re: Binary Counter IP

Hi markg@prosensing.com,

Probably in reality ASYNC_REG didn' t work. I attached a picture of routed design. I don' t know much about this part but looks the issue you mentioned. On the right, as I understand small white and red dots show the location of signals(?) and they don' t look that much close. 

I did simulations in the beginning and then built a system which works almost perfect when only one channel used. There is 1 Hz variation over an hour of measurement for a 9 MHz signal source. Additional signal input to other 3 channels destroy the complete measurement even I apply the same source.

I' m thinking about the signal cabling for input to the FPGA, in case of any external effect. But so far I didn' t observe such an issue. Because as I said single source to any one of 4 channels works perfect! Problem starts after additional signal connection.

 

DesignRoute.png
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Registered: ‎06-21-2017

Re: Binary Counter IP

Can you try making PCNT and SCNT signals instead of variables?

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Teacher drjohnsmith
Teacher
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Registered: ‎07-09-2009

Re: Binary Counter IP

@bruce_karaffa 

Dohh..

I missed that.

Yes, Dont use variables, ....

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Registered: ‎01-22-2015

Re: Binary Counter IP

@macellan85 

     Probably in reality ASYNC_REG didn' t work.
We can revisit this later. 

     When I apply a signal to one channel of a multi channel counter system, I observe counts on the empty channels.  When I load all channels I observe a big shift and some oscillation on the counts.  …single source to any one of 4 channels works perfect! Problem starts after additional signal connection.
This sounds like a hardware problem – and not a problem with the VHDL.

Some questions for you:

1) By “4 channels”, I assume you have four pulsed-signals entering your FPGA board on four connectors, routed through four digital buffers, entering the FPGA through four pins, and routed to four instances of the pulse-counter?

2) What testing have you done to look for cross-coupling between the “4 channels”.   For example, when you input a pulsed-signal on only one channel, does oscope probe on output of digital buffer show pulses on unconnected channels? 

3) Do you terminate inputs on unconnected channels?

4) Have you experimented with different grounding methods between FPGA board, pulsed-signal sources, and board power supply?

5) Are the pulsed-signals differential (LVDS) or single-end?

6) Please describe hardware used to bring the main logic-clock into your FPGA.

7) Is this an old board with decoupling capacitors on the digital buffers and on the FPGA that may have degraded over time?

Adventurer
Adventurer
909 Views
Registered: ‎01-05-2017

Re: Binary Counter IP

Dear markg@prosensing.com  sorry for the delay. You can find the asnwers below for your questions...

 


Some questions for you:

1) By “4 channels”, I assume you have four pulsed-signals entering your FPGA board on four connectors, routed through four digital buffers, entering the FPGA through four pins, and routed to four instances of the pulse-counter?


 

This is a 4-Channel counter design... I' m trying to measure the frequency of 4 different sources. I run the system with 100MHz clock and trying to measure a 10 MHz frequency with 1-2kHz possible variations that I want to detect. Each counter works indepenedently and includes an edge detector (buffer?). Although the signal is not square it works very well for 1 channel!

 


2) What testing have you done to look for cross-coupling between the “4 channels”.   For example, when you input a pulsed-signal on only one channel, does oscope probe on output of digital buffer show pulses on unconnected channels? 

When I connect the oscilloscope probe to the unconnected channels, I observed a signal with 100mV DC offset and 100 mV amplitude. Its shape is terrible but I could calculate the period and then the frequency.  It is the same input signal applied.

 

3) Do you terminate inputs on unconnected channels?


I connected 1k and 50 ohm resistors and 100pF capacitor (each, one by one) parallel to gnd. I didn' t observe a significant change but only the DC offset decreased.

 


4) Have you experimented with different grounding methods between FPGA board, pulsed-signal sources, and board power supply?

 Yes, I tried but no significant change.

 


5) Are the pulsed-signals differential (LVDS) or single-end?


Single ended

 


6) Please describe hardware used to bring the main logic-clock into your FPGA.


You mean the system clock in FPGA?
I used the clock wizard to generate 100MHz clock from the 12MHz on board clock source.

 


7) Is this an old board with decoupling capacitors on the digital buffers and on the FPGA that may have degraded over time?


I don' t know how to check the decoupling capacitors exist or not but this is a spartan 3AN board I bought in 5 years period, not earlier.

 

So problem still keeps itself ...

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878 Views
Registered: ‎01-22-2015

Re: Binary Counter IP

@macellan85 

     

     Maybe my board is not capable of doing this. It is a very basic version (Elbert v2 - Spartan 3AN)…

I find that IO connectors on this board feed the FPGA pins directly!  That is, this board has no digital buffer ICs!!  

Q1. Please show us an oscope view of one digital pulse as it appears at the FPGA input pin?

 

     This is a 4-Channel counter design...

In your 09-05-2019 post you show us the VHDL component called Pulse_Counter_4.  This component can count pulses on the one input called “Pulse”. 

Q2. So, to make a “4-Channel counter”, are you instantiating Pulse_Counter_4 four times?

 

The Spartan-3AN has four (I think) IO banks. 

Q3. Are the four pulsed-signals entering the FPGA on pins that are all in the same IO bank?

Q4. Can you bring the four pulsed-signals into the FPGA via pins that are in separate IO banks? – to see if this affects interference between pulsed-signals?

Q5. Please tell us the names of the FPGA pins that receive the four pulsed-signals – and the IO standard you are using for these pins (eg. LVCMOS33?)

Q6. Please show us photographs of the top and bottom sides of your board.

Adventurer
Adventurer
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Registered: ‎01-05-2017

Re: Binary Counter IP

markg@prosensing.com 

 


 Q1. Please show us an oscope view of one digital pulse as it appears at the FPGA input pin?


Here I attached the pictures. Noisy picture shows the unconnected pin. Last time when I checked it was more like a signal but this one looks more terrible. But when I stop the stream on scope, period is still clearly visible.

Q2. So, to make a “4-Channel counter”, are you instantiating Pulse_Counter_4 four times?


Yes, that is correct. I' m using the same design just named as Pulse_Counter_1, 2, 3 and 4. All are totally same design.


The Spartan-3AN has four (I think) IO banks. 

Q3. Are the four pulsed-signals entering the FPGA on pins that are all in the same IO bank?

Q4. Can you bring the four pulsed-signals into the FPGA via pins that are in separate IO banks? – to see if this affects interference between pulsed-signals?


Depending on the Elbert v2 schematics I think the same as you. On page 2, there are 4 banks.

I also thought to use different banks for each input but there is no gpio connection for BANK 1 and 2. Then I applied two inputs to BANK 0 and 3, this didn' t produce a better result as well.


Q5. Please tell us the names of the FPGA pins that receive the four pulsed-signals – and the IO standard you are using for these pins (eg. LVCMOS33?)


I attached the complete constraint file, just changed the extension since the site doesn' t accept .ucf file

Q6. Please show us photographs of the top and bottom sides of your board.


Attached some more pictures ...

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Teacher drjohnsmith
Teacher
839 Views
Registered: ‎07-09-2009

Re: Binary Counter IP

your bottom trace is less than 400 mV PkPk
that is just very bad noise,
its not a signal that should be going into the fpga or come out of it
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Registered: ‎01-22-2015

Re: Binary Counter IP

@macellan85 

I understand that your first oscope photo shows the current “digital” waveform input to the FPGA.  If my understanding is correct, then this waveform is a problem for the following reasons:

1) You have specified the FPGA input to use LVCMOS33 logic which has VIH=2.0 and VIL=0.8 (table 35, DS099).  Your digital waveform with ramped transitions between VIH and VIL will cause the FPGA digital input buffers to oscillate.  These oscillations can be “seen” by your VHDL pulse counter and interpreted as false pulses.

2) The max/min levels for your digital waveform approach the absolute maximum values (4.3V, -0.85V) for the Spartan-3 (see table 28, DS099).

Please consider using an external circuit (eg. high-speed comparator) to transform your current digital waveform into a proper digital waveform (0.0-3.3V, w/fast transitions) – and then send this proper digital waveform to the FPGA.

 

791 Views
Registered: ‎01-22-2015

Re: Binary Counter IP

@macellan85 

Try the following...

Use your test equipment to generate a proper 0-3.3V digital square-wave.  Feed this square-wave to the Elbert board and check whether your multichannel pulse counter is working properly.

Adventurer
Adventurer
784 Views
Registered: ‎01-05-2017

Re: Binary Counter IP

Dear markg@prosensing.com 

That' s what I want to do right now but the problem is I don' t have such a signal generator :) 

I have a source for 2kHz. When I connect it to the one or two channels, I observed a very small 10mVpp signal on the unconnected channels. In case of counts, I see the correct values on input channels and 0 on the other channels. Now I want to test it using a MHz square signal source. 

I' ll let you know once I did it.

Thank you 

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Adventurer
Adventurer
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Registered: ‎01-05-2017

Re: Binary Counter IP

Dear markg@prosensing.com 

Eventually I got a Function Generator and performed a series of tests as summarised below. 

1. FG -> Stable and correct freq.value

2. FG+MD (mydevice) -> Stable and correct freq. value for both channels 

3. FG + MD1 + MD2 (MDs powered from ext. power source) -> FG stable and correct freq value but MDs not! (Current consumptions MD1: 6.1mA, MD2: 5.2 mA, when they both are connected to the FPGA 0.5 mA increase observed in total currrent) 

4. FG+MD1 x 2 (MD1 connected to two channels) -> All stable and correct freq values observed

5. FG+MD1+MD2 (MDs powered from FPGA 3.3V and GND pins, waveform is the same as before) -> FG stable and correct freq value but MDs not!

 

So this looks the problem arises from the MDs. I thought there can be a loading problem but the current consumption doesn' t support this idea. So maybe a kind of interference issue through power lines of MDs ... At least FPGA board looks capable of counting MHz levels in parallel.

 

 

 

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Highlighted
627 Views
Registered: ‎01-22-2015

Re: Binary Counter IP

@macellan85 

Thanks for getting back to us with the good news!  I've enjoyed working with you.  Let us know if you need help solving other problems.

Mark

Adventurer
Adventurer
556 Views
Registered: ‎01-05-2017

Re: Binary Counter IP

markg@prosensing.com 

Nice to hear that Mark. Thank you for your support.

Best wishes ...

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