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Visitor mehdiab
Visitor
4,473 Views
Registered: ‎05-04-2011

Bitgen internal error

Hello,

I use fpga_editor to do some post-par fixes, like creating a output pad and connecting signals to it in order to use them on board. In this case, I want to add the output pad coined "XL_96_BIS" at site "R3". Bitgen DRC runs fine but when I run bitgen, I get the following message:

 

Creating bit map...
INTERNAL_ERROR:Bitgen:BsRain_Bfd.c:909:1.104.12.1 - Master site IOB_X2Y262 is
   unused for slave comp XL_96_BIS
FATAL_ERROR:Bitgen:BsRain_Bfd.c:2283:1.104.12.1 - Conflicting OSTANDARD found
   for comp "XL_96_BIS" ("LVCMOS33" vs. "OFF")   Process will terminate. For
   technical support on this issue, please open a WebCase with this project
   attached at http://www.xilinx.com/support.
ERROR: bitgen crashed with error code 1

 

Has anyone faced this kind of issue? Is there any known workaround?

 

Thanks in advance and best regards,

 

Mehdi

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4 Replies
Xilinx Employee
Xilinx Employee
4,463 Views
Registered: ‎07-01-2008

Re: Bitgen internal error

A CR was filed some time ago with the same errors on a Virtex-5 design. It was closed with the following comments regarding it being an invalid design:

 

"Not a bug. You created an IOBS comp for the single ended standard LVCMOS33. You should use an IOB comp for single ended standards, not an IOBS."

 

"Invalid design. An IOBS comp is expected to be paired with an IOBM comp and used for differential output signals."

 

So it seems you have created an IOBS instead of an IOB with your manual edits. Try changing it to an IOB.

Visitor mehdiab
Visitor
4,447 Views
Registered: ‎05-04-2011

Re: Bitgen internal error

Hi bwade,

 

thanks for your answer. Indeed,  I was instantiating an IOBS in my script. In case it may help understanding the issue, this is the part remated to this IOB instantiation:

#add -s "R3" comp "XL_96"
add -s "R3" -t "IOB" comp "XL_96"
setattr comp "XL_96" Config     "OUSED:0 OUTMUX:0 TUSED:0"
setattr comp "XL_96" Drive      "12"
setattr comp "XL_96" Ostandard  "LVCMOS33"
setattr comp "XL_96" Slew       "SLOW"

An then I connects its ports. DRC showes no error.

 

So I tried your suggestion, but then I get the following error message:

 

add -s "R3" -t "IOB" comp "XL_96"
ERROR:FPGAEditor:137 - The site in the selection or specified with the "-s" switch is not consistent with the comptype specified with the "-t" switch.

 

I also tried not to specify the arguments <-t "IOB">, but then I get the same error message as in my first message during bitgen run.

 

By the way, I have searched ug190 and virtex5_hdl documentation for information about the differences between IOB, IOBs and IOBM and in which case to instantiate each of them, but I could not find any clue. Could you please indicate me where to find such information?

 

Best regards,

 

Mehdi

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Visitor mehdiab
Visitor
4,446 Views
Registered: ‎05-04-2011

Re: Bitgen internal error

I forgot to add that I do not intend to instantiate differential output signals.
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Visitor mehdiab
Visitor
4,425 Views
Registered: ‎05-04-2011

Re: Bitgen internal error

After some trials, I noticed that I have this issue only when try to add IOBs on sites that have N_CC capability. So it seem indeed linked to differential clock signals. As I do not want to use the clock capability of this site nor its differential capability, does anyone has an idea how to instantiate with fpga_editor a regular IOB on such a site?

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