I am working on the getting started design tutorial (FMC-HDMI-CAM + PYTHON-1300-C) for zynq board. This tutorial is for the vivado's version 2014.4, but I use vivado 2015.3.
I could create the block design and the synthesis was complete, but the implementation failed writing the following error :
How can I resolve this in my project?
Thanks a lot.
From the error message, I believe the error is from FIFO IP. Check if the IP has been instantiated correctly.
Did you set OOC run for the IP? Check if the OOC run was successful and If you are correctly able to see all the files in Sources window after Expanding.
Also since the tutorial is for Vivado 2014.4, try using the same vivado version.
Can you provide any update on this forum thread??