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armic
Observer
Observer
10,439 Views
Registered: ‎01-10-2013

Buffered clock IO's - Implementation problem

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I recently drafted an MMCM block with two differential (LVDS 25) clock inputs . The block synthesised without a hitch .Once implementation started a [Place 30-188] error was shown saying that the input clock was unbuffered (even though a synthesised schematic view shows the ibufs are indeed there).

 

Seeing this I Implemented an IBUFDS in the top file, yet once I run implementation a new error is shown saying that there are now two buffers connected in series !! [Drc 23-20]. This is quite confusing since there seems to be no middle ground between those two error generating scenarios. 

 

Is there any way out of this problem?

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vemulad
Xilinx Employee
Xilinx Employee
11,793 Views
Registered: ‎09-20-2012

Hi,

 

In case if you used Clocking wizard IP, it creates input buffers based on "source" setting.

 

Untitled.png

 

If you are manually instantiating the input buffers then you can set this to NONE to prevent tool inserting buffer.

 

Thanks,

Deepika.

Thanks,
Deepika.
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5 Replies
vemulad
Xilinx Employee
Xilinx Employee
10,430 Views
Registered: ‎09-20-2012

Hi,

 

Are you inserting MMCM using clocking wizard IP in the design?

 

Open synthesized design and check the connectivity of ports/buffers mentioned in the error.

 

Please show us the schematic of this ports so that we can comment.

 

Thnaks,

Deepika.

Thanks,
Deepika.
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venkata
Moderator
Moderator
10,412 Views
Registered: ‎02-16-2010
which VIVADO version you are using?
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armic
Observer
Observer
10,401 Views
Registered: ‎01-10-2013

Thanks for your quick replies. I'm using vivado 2014.2 (which is causing quite some strange and unexplainable problems lately). I also instantiated the MMCM using Xilinx's own IP. I managed to partly solve the problem using the following two methods:

 

1) Since I needed everything to be in the same clock tile I instantialed a PLLE as a crude buffer, or
2) Removed the buffering from the input clocks (and changed them to single ended). Then I took the differential input and passed them through an IBUFDS to change the differential signal to a single ended one. 

 

Needless to say the second option is much better (and much more resource efficient). Yet it still proved to be somewhat problematic, forcing me to use the CLOCK_DEDICATED_ROUTE FALSE property (even though all components are in the same clock tile).

 

Regards

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vemulad
Xilinx Employee
Xilinx Employee
11,794 Views
Registered: ‎09-20-2012

Hi,

 

In case if you used Clocking wizard IP, it creates input buffers based on "source" setting.

 

Untitled.png

 

If you are manually instantiating the input buffers then you can set this to NONE to prevent tool inserting buffer.

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

View solution in original post

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armic
Observer
Observer
10,389 Views
Registered: ‎01-10-2013

Sure, that's the same exact thing I did in the latter solution. Instead of leaving it to the synthesiser to add the buffers I added them myself . However its still confusing because the orIginal problem shouldn't have happened (using bufs generated by the IP). Thanks for your help and timely responses :)

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